The Xilinx chip needs to be configured with the appropriate software. The configuration is developed at Oak Ridge, and the product is a file of bits that need to be downloaded via the Xilinx serial link to the HM board. The file is an ascii file, containing about 180K bits.
Figure 2: Timing of the Xilinx serial signals
Figure 2 shows the timing of the Xilinx serial signals. Initially, the xil_prog and xil_sclk lines are set and reset on timescales of tens of msec. After that, the data are clocked in as fast as the program will run, on the rising edge of the clock, as indicated. After the data are done, the clock line is wiggled 20 times for good measure. The `done' line should come up at the end when all is done. This line is not brought out on a connector. I reset the data line at the end. The xil_prog line must be kept low. If it is allowed to go high, the program is lost and needs to be reloaded again. Note that the xil_ lines reside on J8, where the mode lines and the trigger line are housed. Care must be taken to not affect the xil_prog line when manipulating these other signals.
The downloading process is slow, since one bit at a time is transferred from the HP over the net to VME, and from there to the LeCroy 2366 communications board, and from there to the HM. It takes about 20 minutes to download the bits. If the downloading is successful, 12 LEDs on the little diagnostic board all go out. There are several solutions to the speed problem:
1) one can have the software on the HP download a 24 bit-word to the LeCroy 2366, and have the 2366 reprogrammed so that it ships them out serially. This would speed up the process by a factor of 24 to under 1 minute. This would require the Oak Ridge Xilinx programmers to design such a configuration. It is on their list of things to do, but not near the top.
2) one can write a program in C, which executes in the VME cpu, which reads the file and loads the bits. This would completely get rid of all the network overhead and run extremely fast.