Type 4:
This is the configuration that has been explored so far. It is a
descendent of the fvtx detector, with one plane as close to the vertex as
possible. sili_endcap_zldrd = 20.50, 25.83, 31.06, 36.30 cm. Number of 8-chip modules: 12, 20, 20, 20 Although not shown in this view, the model contains the beam pipe, the central barrels (carbon supports, silicon and cooling tubes), carbon support cage and cables, and in the endcap region 3mm carbon panels supporting the 8-chip modules made of 300µm silicon. | |
Running in cvs5, cfmgmc_sep28.input =
5. 5.0 18.0 90.0 14.0 100 0.0 0.0 0.0 0.0 (this is 5 Gev muons sprayed into the North arm) ancsvx_type4_01.root, analyzed with resolution_both.C, and plotted with res_cluster_both.C Type 4 z-vertex resolution = 184 µm
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Using pythia file
/phenix/data02/rhphemds/events/hjievt_600auaucentsq08_042298.dat → PISAEvent_type4_29sep06.root → ancsvx_type4_29sep06.root I ran 11 central AuAu Pythia events. This plot shows the hits in a side view of the silicon detector. You can see the barrels, and the 4 endcap layers, with 8-chip modules placed on the front and back of an (invisible) support structure. The inset shows the bottom of the first station, and the blue arrow points at the lowest 8-chip module. | |
This is a front (x-y) view of the 8-chip module pointed out in the
figure above. There are 313 entries for 11 events in this plot. The modules
measure
7.36×0.64 cm, for a mean track density of 6.0±0.3per cm²
per event in central AuAu events.
Taking the active area of a single chip (≅0.6×0.8 cm), 22×128 = 2816 pixels per chip, and a mean number of pixels per track of 2.78 (see picture above) gives 8.0 pixels on per fpix chip per central AuAu collision, for the busiest module in the detector. Central AuAu ccupancy is therefore 8/2816 = 0.28%. The averages for the whole first plane (12 8-chip modules) are a factor of 2.25 less, or 3.6 pixels on per chip per central collision.
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Across the 8-chip module, there is a weak dependence vs. x, with the central chips tending to be busier, as shown by the fit. For the current runs, the counts are statistics-limited. | |
records per event for the busiest 8-chip module, for 110 consecutive min-bias AuAu events. | |
This is the distribution of record numbers in the previous plot, on a log scale, with an exponential fit in red. If the exponential holds, this plot can be used to estimate the probability for any occupancy, recalling that the mean is 8 hits for the busiest chip | |
AuAu min bias
PISAEVENT_auauminbi.root, and ancsvx_auauminbi.root, from pythia file /phenix/data11/rhphemds/run2/hijing/ hji135evt_20000auauminb200sq01_060602.dat I ran 11 minbi AuAu Pythia events. This shows the hits in a side view of the silicon detector. You can see the barrels, and the 4 endcap layers, with 8-chip modules placed on the front and back of an (invisible) support structure. The inset shows the bottom of the first station, and the blue arrow points at the lowest 8-chip module. | |
This is a front (x-y) view of the 8-chip module pointed out in the
figure above. There are 763 entries for 110 events in this plot. The modules
measure
7.36×0.64 cm, for a mean track density of 1.47±0.05 per cm²
per event.
The average for the whole 12-module first plane is down by a factor 2.09 from that of the busiest module, for these minbias events.
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pp 'min bias'
using /phenix/data11/rhphemds/Run02/simProject29/event/
PYTHIA_MinbPP-0000035040-00029.dat |
system | station 1, 8-chip module 1 | station 1 all 12 modules | ||
---|---|---|---|---|
Track density (/cm²) | pixels on per chip | Track density (/cm²) | pixels on per chip | |
AuAu central (b<2fm) | 6.0 | 8.0 | 2.7 | 3.6 |
AuAu min bias | 1.47 | 1.96 | 0.70 | 0.94 |
pp 'min bias' | 0.0160 | 0.0210 | 0.0067 | 0.0090 |