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Trigger/Reset coincidence:
When the preamp/integrator gets reset every 1K (2K,4K,8K) clocks, it's signal
does not simply drop to zero, rather it tends to 'ring' before zeroing (see
the "noise and reset" figure).
Since the trigger occurs randomly relative to the clock, it is possible that
the two occur simultaneously, in which case the ADC will digitize the
excursions of the reset pulse and not the charge deposited in that event.
To measure how often this occurred, we recorded the time of each trigger
relative to the reset pulse. This value was used to create the plot of
double subtracted data vs. clock cycle at left. The dense central band is
the pedestal, with a smear of real signals above. The light bands at +/- 300
ADC channels indicate that occasionally an erroneous pre- or post-sample signal of zero
is being returned. The thin smattering on the right indicates that occasionally
the clock is not resetting properly. The small vertical distribution on the
left edge (time = 0) shows that simultaneous trigger and reset pulses are
rare enough to be negligable.
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