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All functions of the mother board have been tested. The Summary of results is as follows.

1. The resistances of the passing-through signal lines ranged 0.1 - 2.2 ohm. Some AGNDs(pin# 106,110,114,118,122,126 on 160pin JAE-KX-14 connector) and DGNDs(pin# 102 on JAE-KX-14 connector) were found not to be connected to ground.

2. Capacitors at the output stages of LDO voltage regulators for -5VA were found to be mounted with the wrong polarity and remounted. All LDO voltage regulators showed good performance. The poly-fuses at the input stages were working and the fluctuation of LDO voltage regulator outputs from the target voltage were less than 1.2%.

3. All spy channels were working. The analog spy output was inverting the input signal with an approximate gain of 0.88. It showed a linear response for input amplitudes up to 5V.

4. We verified that 93 multiplexed serial readout channels of MAX186 ADCs for various monitoring voltages could turn out some ADC values. But we obtained an abnormal ADC response. Further tests on ADC response are necessary.

5. PECL clock generator and fanout chips on the mother board were tested at 38MHz, 4 X Beam clock frequency. For the 38MHz TTL input, the generated PECL clocks swung from 3.1V to 3.9V with 38MHz frequency.

References.

1. The Design,Layout and Testing of the Multiplicity Vertex Detector(MVD) Motherboard
   Sangkoo Hahn, LeRoy Cope, Jan Boissevain, and Gary Smith
   PHENIX-MVD-98-21, PHENIX Note 350
   http://p2hp2.lanl.gov/phenix/mvd/notes/1998/PHENIX-MVD-98-21/motherboard.html
2. Chain test note
   Hubert van Hecke
   Submitted January 23, 1998
   http://p2hp2.lanl.gov/people/hubert/talks/chain/mother.html
3. Signal Assignments for MVD Connectors and Cables
   Jan Boissevain, Sangkoo Hahn, and Roy Cope
   PHENIX-MVD-98-20, PHENIX Note 349
   http://p2hp2.lanl.gov/people/hubert/talks/chain/signals.html
4. Data sheet of the ADG406, Analog Devices, Inc.
5. Data sheet of the MAX186 ADC, Maxim Integrated Product.