This is a semi-automatic translation of an original Word document. Translation 16 Sep 98 HvH

Design, Layout and Testing of the PHENIX/MVD Power-Communication and Daughter Boards

 

Sangkoo Hahn, Roy Cope and Jan Boissevain

 

PHENIX-MVD-98-31, PHENIX Note 360

1. Introduction

 

Six Power-Communication (power-comm for short (4 ohms or less)) boards and one Daughterboard are plugged into one Motherboard (http://p2hp2.lanl.gov/phenix/mvd/notes/1998/PHENIX-MVD-98-21/motherboard.pdf) bridging signals, power and returns to/from the motherboard and the Multi-Chip Modules (MCMs). Thus, a major portion of the board area is dedicated for interconnection traces, but there are some buffers on board for high-fidelity, high frequency signals. The buffers are located on these boards to lower the power consumption on the MCMs and also to reduce the amount of interference on sensitive preamplifier inputs of the MCM by physically placing the signal drivers for long cables away from MCMs. The power-comm and the daughter boards are identical in electrical functions, but the daughterboard interfaces with the motherboard with two 80-pin connectors instead of a single 160-pin connector for the power-comm board

(See http://p2hp2.lanl.gov/phenix/mvd/notes/1998/PHENIX-MVD-98-20/cable_conn_master.html for details of the connector types and pin assignments.)

 

A block diagram of the power-comm (identical to daughterboard) is shown in Figure 1. The buffers residing in either the power-comm or daughter boards are;

 

2. Design and Layout

 

<-- xxx -->

For the 38MHz PECL clock fan-out to the AMUADC chips on the MCM, an ECL logic chip 10E111 is used. The chip has nine buffered ECL outputs, of which only the first six are used for the six MCMs. The differential-pair input and outputs signal lines on the board are laid out to maintain 50-ohm strip-line transmission impedance for good signal integrity.

 

The beam clock and 4x beam clock lines going to the Xilinx chips are handled by the ACT logic chips, 74ACT244. Input signals are terminated with 51 ohms, and two chips of 4 outputs are used for the six outputs each. The serial data and control lines to down-load configuration and programming bits of the MCM are buffered. The same chip types are used for driving the mode bits. The serial data from each MCM are read-back for confirmation of proper down-load in similar fashion.

The two MCM output data lines for the mission data carrying the pulse height information of all detector channels, and the data clock are converted into LVDS (low-voltage differential signal) for high noise immunity at low power consumption. Special attention is given to control the characteristic impedance of the transmission line to 50 ohm.

 

Two analog spy channel lines from each MCM are buffered with OP-283 operational amplifiers with a gain of -1 (inverting buffer). The signal bandwidth is enough to process the relatively fast rising edge of the spy signals. The current-sum output signals, one from each MCM, are unity-gain buffered with CLC426. CLC426 has 230MHz gain-bandwidth product, more than enough signal bandwidths for the fast mission signals.

 

 

3. Test Plan

 

3.1 Visual inspection for component placement and assembly quality

 

 

3.2 Test preparation

 

This board has multiple high-density connectors (0.5mm pitch for the MCM cable connectors, 0.8mm pitch Motherboard connector), and it would be most practical to prepare one mating connector of each species (one for the Motherboard connector, one for the MCM connector) with pig-tail wires. An MCM output Kapton cable with a connector head may suffice our need to test the signals on the MCM side connector.

 

It is best to limit the number of mate-demate cycles for the small, high pitch MCM cable connector. Thus it is recommended that all the related tests are done for each MCM connector once it is mated. The following test descriptions reflect such.

 

Test instruments required include a multi-meter, differential pulse generator with variable frequency (up to 40MHz) and rise/fall time adjustments, and three power supplies adjustable between 0V and 5V each.

Note that the following test details mention the connector and pin numbers on the Power-Comm board itself, but actual tests are performed on the fan-out board at corresponding connector pins.

 

3.3 J1 connector tests

 

A. Passive signal test

 

The following tests are for all signal lines that are either directly connected between the MCM connector and Motherboard connector, or there are only resistor/capacitor passive components between them. The measurements are done with an ohm-meter across the two pins designated as below. Resistance is in ohms, and should be within +/-10% of the nominal values as shown.

 

Plug in the pig-tailed connector head on the MCM side on J1. Connect the pig-tailed connector head on the Motherboard side on J13, and verify the following. The J1 pin-3, 15 and 19 have higher resistances than others because of their lengths and single-trace connections.

 

From

To

Measurements

Notes

J1 Pin Number

J13 Pin Number

 . .

1

149

10k

Silicon detector bias line

3

150

short (4 ohms or less)

Silicon detector bias line return

4

120

short (4 ohms or less)

+5V analog for TGV32

5

118

short (4 ohms or less)

+5V analog return for TGV32

8, 17

118

short (4 ohms or less)

+5V analog return

9

108

short (4 ohms or less)

+5V analog for comparator

10

106

short (4 ohms or less)

+5V analog return for comparator

11

120

short (4 ohms or less)

+5V analog for AMUADC

12

118

short (4 ohms or less)

+5V analog return for AMUADC

13

130

short (4 ohms or less)

-5V analog

14

136

short (4 ohms or less)

+2.5V analog

15

142

short (4 ohms or less)

Temp sensor

19

55

short (4 ohms or less)

Serial_Enable (reset)

27

103

short (4 ohms or less)

+5V digital

28

101

short (4 ohms or less)

+5V digital return

29

104

short (4 ohms or less)

+5V digital

30, 38, 40, 42

101 or 102

short (4 ohms or less)

+5V digital return

44, 46, 48

101 or 102

short (4 ohms or less)

+5V digital return

 

 

B. Active signal tests

 

B.1. Preamp and AMUADC spy channel signal buffer tests

 

Connect +5V analog power supply to J13-P120 and a separate +5V digital supply to J13-P103 and 104. Also

connect -5V supply to J13-P132. Leave the power supplies connected for all other tests. Connect a pulse generator output of 1.0Vp-p, ~100kHz square pulse with rise and fall times of approximately 250ns to the input pin. Monitor the output pin using an oscilloscope as follows.

(Note: for any test hereafter, leave the input stimuli connected after the tests as some of them may be used for the same test of another connector.)

 

Input

Output

Measurements

Note

J1 Pin #

J13 Pin #

    

16

81

Output waveform is inverted with the same amplitude as input

Preamp spy channel

18

82

Output waveform is inverted with the same amplitude as input

AMUADC spy channel

 

B.2. PECL clock line test

 

With the pulse generator used in Test B.1, reset the clock frequency to 40MHz, adjust the pulse output swing between 0 and 5.0V. Connect the two differential outputs of the pulse generator to the two corresponding pins on the fan-out board as on J13. Terminate the two pins with 110-ohm resistors to ground. Terminate the two corresponding output pins on fan-out board as on J1 with 110-ohm resistors to ground. Monitor the voltages at the termination resistors with scope probes. Leave the power supply connections alone for other tests.

 

.

Input

Output

Measurements

Note

J13-13 and 15

J1-49 and 50

Output voltage should have the same waveform of the input with approximately 4.2V for high and 3.4V for low swings

PECL clock line

 

B.3. MCM data drive test

 

With the same pulse generator used in Test B.2, connect single output of the pulse generator to the board inputs as follows. Connect a 110-ohm terminating resistor between the two output pins (not to the ground.) Monitor the voltages at the outputs with scope probes.

 

Input

Output

Measurements

Note

J1 Pin #

J13 Pin #

 . .

39

17, 19

Output voltage should have the same waveform of the input with ~250mVp-p

LVDS clock +/- signal

41

18,20

Output voltage should have the same waveform of the input with ~250mVp-p

LVDS data #1 +/- signal

43

21,23

Output voltage should have the same waveform of the input with ~250mVp-p

LVDS data #2 +/- signal

 

B.4. Mode bit and LVL_1_Accept test

 

With the pulse generator used in Test 1, reset the clock frequency to 10MHz, and connect the output to the board inputs as follows. Monitor the voltages at the outputs with scope probes.

 

Input

Output

Note

 .
J13 Pin # J1 Pin # . .
1 31 Output voltage should have the same waveform of the input with ACT logic output levels (0-5V) Mode bit 0
2 32 Output voltage should have the same waveform of the input with ACT logic output levels (0-5V) Mode bit 1
3 33 Output voltage should have the same waveform of the input with ACT logic output levels (0-5V) Mode bit 2
4 34 Output voltage should have the same waveform of the input with ACT logic output levels (0-5V) Mode bit 3
5 35 Output voltage should have the same waveform of the input with ACT logic output levels (0-5V) Mode bit 4
6 36 Output voltage should have the same waveform of the input with ACT logic output levels (0-5V) Mode bit 5
9 37 Output voltage should have the same waveform of the input with ACT logic output levels (0-5V) LVL_1_Accept

 

 

B.5. Serial Clock, Data and Beam Clock test

 

Connect the pulse generator output at 100KHz with logic level swings to the J13 pins and monitor the bits on J1 pins as follows with scope probes.

 

Input

Output

Measurements

Note

J13 Pin #

J1 Pin #

 . .

63

21

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Clock

75

24

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Latch

64

22

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Data_in

14

47

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM1_38MHz

18

45

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM1_9.5Mhz

 

Input

Output

Measurements

Note

J1 Pin #

J13 Pin #

 . .

23

67

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Ser_Data_Out_MCM1

 

 

B.6. Program, Readback and Reset test

 

Connect the pulse generator output at 100KHz with logic level swings to the J13 pins and monitor the bits on J1 pins as follows.

 

Input

Output

Measurements

Note

J13 Pin #

J1 Pin #

 . .

76

20

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Readback

77

25

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Program_in

78

26

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM Reset

 

 

B.7. Discriminator Sum test

 

Connect a pulse generator output of 10MHz, 1.0Vp-p square pulse to the input of J1 pins and monitor the output at J13 pins as follows.

 

Input

Output

Measurements

Note

J1 Pin #

J13 Pin #

 . .

7

95

Output voltage should have the same waveform of the input

Discriminator sum output

 

B.8. Blank pins

 

These two pins, J1-2, J1-6, should have no connections to anywhere.

 

 

3.4 J2 connector tests

 

A. Passive signal test

 

Plug in the pig-tailed connector head on the MCM side on J2. Connect the pig-tailed connector head on the Motherboard side on J13, and verify the following.

 

From

To

Measurements

Notes

J2 Pin Number

J13 Pin Number

 . .
. . . .

1

151

10k

Silicon detector bias line

3

152

short (4 ohms or less)

Silicon detector bias line return

4

120

short (4 ohms or less)

+5V analog for TGV32

5

118

short (4 ohms or less)

+5V analog return for TGV32

8, 17

94

 .

+5V analog return

9

108

short (4 ohms or less)

+5V analog for comparator

10

106

short (4 ohms or less)

+5V analog return for comparator

11

120

short (4 ohms or less)

+5V analog for AMUADC

12

118

short (4 ohms or less)

+5V analog return for AMUADC

13

130

short (4 ohms or less)

-5V analog

14

136

short (4 ohms or less)

+2.5V analog

15

144

short (4 ohms or less)

Temp sensor

19

56

short (4 ohms or less)

Serial_Enable (reset)

27

111

short (4 ohms or less)

+5V digital

28

107

short (4 ohms or less)

+5V digital return

29

104

short (4 ohms or less)

+5V digital

30, 38, 40, 42

105 or 109

short (4 ohms or less)

+5V digital return

44, 46, 48

105 or 109

short (4 ohms or less)

+5V digital return

 

 

B. Active signal tests

 

B.1. Preamp and AMUADC spy channel signal buffer tests

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J2 Pin #

J13 Pin #

 . .

16

83

Output waveform is inverted with the same amplitude as input

Preamp spy channel

18

84

Output waveform is inverted with the same amplitude as input

AMUADC spy channel

 

B.2. PECL clock line test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J13-13 and 15

J1-49 and 50

Output voltage should have the same waveform of the input with approximately 4.2V for high and 3.4V for low swings

PECL clock line

 

B.3. LVDS (MCM data drive) test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J2 Pin #

J13 Pin #

 . .

39

22, 24

Output voltage should have the same waveform of the input with ~250mVp-p

LVDS clock +/- signal

41

25, 27

Output voltage should have the same waveform of the input with ~250mVp-p

LVDS data #1 +/- signal

43

26, 28

Output voltage should have the same waveform of the input with ~250mVp-p

LVDS data #2 +/- signal

 

B.4. Mode bit and LVL_1_Accept test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J13 Pin #

J2 Pin #

 . .

1

31

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 0

2

32

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 1

3

33

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 2

4

34

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 3

5

35

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 4

6

36

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 5

9

37

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

LVL_1_Accept

 

B.5. Serial Clock, Data and Beam Clock test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J13 Pin #

J2 Pin #

 . .

63

21

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Clock

75

24

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Latch

64

22

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Data_in

14

47

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM_38MHz

18

45

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM_9.5Mhz

Input

Output

Measurements

Note

J2 Pin #

J13 Pin #

 . .

23

68

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Ser_Data_Out_MCM

 

B.6. Program, Readback and Reset test

 

Connect the pulse generator output with logic level swings to the J13 pins and monitor the bits on J2 pins as follows.

 

Input

Output

Measurements

Note

J13 Pin #

J2 Pin #

 . .

76

20

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Readback

77

25

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Program_in

78

26

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM Reset

 

B.7. Discriminator Sum test

 

Connect a pulse generator output of 10MHz, 1.0Vp-p square pulse to the input of J2 pins and monitor the output at J13 pins as follows.

 

Input

Output

Measurements

Note

J2 Pin #

J13 Pin #

 . .

7

96

Output voltage should have the same waveform of the input

Discriminator sum output

 

B.8. Blank pins

 

These two pins, J2-2, J2-6, should have no connections to anywhere.

 

 

3.5 J3 connector tests

 

A. Passive signal test

 

Plug in the pig-tailed connector head on the MCM side on J3. Connect the pig-tailed connector head on the Motherboard side on J13, and verify the following.

 

From

To

Measurements

Notes

J3 Pin Number

J13 Pin Number

 . .
. . . .

1

153

10k

Silicon detector bias line

3

154

short (4 ohms or less)

Silicon detector bias line return

4

124

short (4 ohms or less)

+5V analog for TGV32

5

122

short (4 ohms or less)

+5V analog return for TGV32

8, 17

93

short (4 ohms or less)

+5V analog return

9

112

short (4 ohms or less)

+5V analog for comparator

10

110

short (4 ohms or less)

+5V analog return for comparator

11

124

short (4 ohms or less)

+5V analog for AMUADC

12

122

short (4 ohms or less)

+5V analog return for AMUADC

13

132

short (4 ohms or less)

-5V analog

14

138

short (4 ohms or less)

+2.5V analog

15

145

short (4 ohms or less)

Temp sensor

19

57

short (4 ohms or less)

Serial_Enable (reset)

27

119

short (4 ohms or less)

+5V digital

28

117

short (4 ohms or less)

+5V digital return

29

115

short (4 ohms or less)

+5V digital

30, 38, 40, 42

113 or 117

short (4 ohms or less)

+5V digital return

44, 46, 48

113 or 117

short (4 ohms or less)

+5V digital return

 

 

B. Active signal tests

 

B.1. Preamp and AMUADC spy channel signal buffer tests

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J3 Pin #

J13 Pin #

 . .

16

85

Output waveform is inverted with the same amplitude as input

Preamp spy channel

18

86

Output waveform is inverted with the same amplitude as input

AMUADC spy channel

 

 

B.2. PECL clock line test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J13-13 and 15

J3 -49 and 50

Output voltage should have the same waveform of the input with approximately 4.2V for high and 3.4V for low swings

PECL clock line

 

B.3. LVDS (MCM data drive) test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J3 Pin #

J13 Pin #

 . .

39

29,31

Output voltage should have the same waveform of the input with amplitudes of ~250mVp-p

LVDS clock +/- signal

41

30,32

Output voltage should have the same waveform of the input with amplitudes of ~250mVp-p

LVDS data #1 +/- signal

43

33,35

Output voltage should have the same waveform of the input with amplitudes of ~250mVp-p

LVDS data #2 +/- signal

 

 

B.4. Mode bit and LVL_1_Accept test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J13 Pin #

J3 Pin #

 . .

1

31

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 0

2

32

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 1

3

33

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 2

4

34

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 3

5

35

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 4

6

36

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 5

9

37

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

LVL_1_Accept

 

B.5. Serial Clock, Data and Beam Clock test

 

Connect the pulse generator output with logic level swings to the J13 pins and monitor the bits on J3 pins as follows.

 

Input

Output

Measurements

Note

J13 Pin #

J3 Pin #

 . .

63

21

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Clock

75

24

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Latch

64

22

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Data_in

14

47

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM_38MHz

18

45

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM_9.5Mhz

Input

Output

Measurements

Note

J3 Pin #

J13 Pin #

 . .

23

69

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Ser_Data_Out_MCM

 

 

B.6. Program, Readback and Reset test

 

Connect the pulse generator output with logic level swings to the J13 pins and monitor the bits on J3 pins as follows.

 

Input

Output

Measurements

Note

J13 Pin #

J3 Pin #

 . .

76

20

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Readback

77

25

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Program_in

78

26

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM Reset

 

 

B.7. Discriminator Sum test

 

Connect a pulse generator output of 10MHz, 1.0Vp-p square pulse to the input of J3 pins and monitor the output at J13 pins as follows.

 

Input

Output

Measurements

Note

J3 Pin #

J13 Pin #

 . .

7

97

Output voltage should have the same waveform of the input

Discriminator sum output

 

B.8. Blank pins

 

These two pins, J3 -2, J3 -6, should have no connections to anywhere.

 

3.6 J4 connector test

 

A. Passive signal test

 

Plug in the pig-tailed connector head on the MCM side on J3. Connect the pig-tailed connector head on the Motherboard side on J13, and verify the following.

 

From

To

Measurements

Notes

J4 Pin Number

J13 Pin Number

 . .

1

155

10k

Silicon detector bias line

3

156

short (4 ohms or less)

Silicon detector bias line return

4

124

short (4 ohms or less)

+5V analog for TGV32

5

122

short (4 ohms or less)

+5V analog return for TGV32

8, 17

94

short (4 ohms or less)

+5V analog return

9

112

short (4 ohms or less)

+5V analog for comparator

10

110

short (4 ohms or less)

+5V analog return for comparator

11

124

short (4 ohms or less)

+5V analog for AMUADC

12

122

short (4 ohms or less)

+5V analog return for AMUADC

13

132

short (4 ohms or less)

-5V analog

14

138

short (4 ohms or less)

+2.5V analog

15

146

short (4 ohms or less)

Temp sensor

19

58

short (4 ohms or less)

Serial_Enable (reset)

27

127

short (4 ohms or less)

+5V digital

28

121

short (4 ohms or less)

+5V digital return

29

121

short (4 ohms or less)

+5V digital

30, 38, 40, 42

125 or 121

short (4 ohms or less)

+5V digital return

44, 46, 48

125 or 121

short (4 ohms or less)

+5V digital return

 

 

B. Active signal tests

 

B.1. Preamp and AMUADC spy channel signal buffer tests

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J4 Pin #

J13 Pin #

 . .

16

87

Output waveform is inverted with the same amplitude as input

Preamp spy channel

18

88

Output waveform is inverted with the same amplitude as input

AMUADC spy channel

 

 

B.2. PECL clock line test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J13-13 and 15

J4 -49 and 50

Output voltage should have the same waveform of the input with approximately 4.2V for high and 3.4V for low swings

PECL clock line

 

B.3. LVDS (MCM data drive) test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J4 Pin #

J13 Pin #

 . .

39

34, 36

Output voltage should have the same waveform of the input with amplitudes of ~250mVp-p

LVDS clock +/- signal

41

37, 39

Output voltage should have the same waveform of the input with amplitudes of ~250mVp-p

LVDS data #1 +/- signal

43

38, 40

Output voltage should have the same waveform of the input with amplitudes of ~250mVp-p

LVDS data #2 +/- signal

 

B.4. Mode bit and LVL_1_Accept test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J13 Pin #

J4 Pin #

 . .

1

31

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 0

2

32

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 1

3

33

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 2

4

34

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 3

5

35

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 4

6

36

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 5

9

37

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

LVL_1_Accept

 

B.5. Serial Clock, Data and Beam Clock test

 

Connect the pulse generator output with logic level swings to the J13 pins and monitor the bits on J4 pins as follows.

 

Input

Output

Measurements

Note

J13 Pin #

J4 Pin #

 . .

63

21

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Clock

75

24

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Latch

64

22

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Data_in

14

47

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM_38MHz

18

45

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM_9.5Mhz

Input

Output

Measurements

Note

J4 Pin #

J13 Pin #

 . .

23

70

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Ser_Data_Out_MCM

 

 

B.6. Program, Readback and Reset test

 

Connect the pulse generator output with logic level swings to the J13 pins and monitor the bits on J4 pins as follows.

 

Input

Output

Measurements

Note

J13 Pin #

J4 Pin #

 . .

76

20

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Readback

77

25

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Program_in

78

26

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM Reset

 

 

B.7. Discriminator Sum test

 

Connect a pulse generator output of 10MHz, 1.0Vp-p square pulse to the input of J4 pins and monitor the output at J13 pins as follows.

 

Input

Output

Measurements

Note

J4 Pin #

J13 Pin #

 . .

7

98

Output voltage should have the same waveform of the input

Discriminator sum output

 

B.8. Blank pins

 

These two pins, J4 -2, J4 -6, should have no connections to anywhere.

 

 

3.7 J5 connector test

 

A. Passive signal test

 

Plug in the pig-tailed connector head on the MCM side on J3. Connect the pig-tailed connector head on the Motherboard side on J13, and verify the following.

 

From

To

Measurements

Notes

J5 Pin Number

J13 Pin Number

 . .
. . . .

1

157

10k

Silicon detector bias line

3

158

short (4 ohms or less)

Silicon detector bias line return

4

128

short (4 ohms or less)

+5V analog for TGV32

5

126

short (4 ohms or less)

+5V analog return for TGV32

8, 17

93

short (4 ohms or less)

+5V analog return

9

116

short (4 ohms or less)

+5V analog for comparator

10

114

short (4 ohms or less)

+5V analog return for comparator

11

128

short (4 ohms or less)

+5V analog for AMUADC

12

126

short (4 ohms or less)

+5V analog return for AMUADC

13

134

short (4 ohms or less)

-5V analog

14

140

short (4 ohms or less)

+2.5V analog

15

147

short (4 ohms or less)

Temp sensor

19

59

short (4 ohms or less)

Serial_Enable (reset)

27

135

short (4 ohms or less)

+5V digital

28

129

short (4 ohms or less)

+5V digital return

29

131

short (4 ohms or less)

+5V digital

30, 38, 40, 42

129 or 131

short (4 ohms or less)

+5V digital return

44, 46, 48

129 or 131

short (4 ohms or less)

+5V digital return

 

 

B. Active signal tests

 

B.1. Preamp and AMUADC spy channel signal buffer tests

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J5 Pin #

J13 Pin #

 . .

16

89

Output waveform is inverted with the same amplitude as input

Preamp spy channel

18

90

Output waveform is inverted with the same amplitude as input

AMUADC spy channel

 

 

B.2. PECL clock line test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J13-13 and 15

J5 -49 and 50

Output voltage should have the same waveform of the input with approximately 4.2V for high and 3.4V for low swings

PECL clock line

 

B.3. LVDS (MCM data drive) test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J5 Pin #

J13 Pin #

 . .

39

41, 43

Output voltage should have the same waveform of the input with amplitudes of ~250mVp-p

LVDS clock +/- signal

41

42, 44

Output voltage should have the same waveform of the input with amplitudes of ~250mVp-p

LVDS data #1 +/- signal

43

45, 47

Output voltage should have the same waveform of the input with amplitudes of ~250mVp-p

LVDS data #2 +/- signal

 

B.4. Mode bit and LVL_1_Accept test

 

Connect the pulse generator output with logic level swings to the J13 pins and monitor the bits on J5 pins as follows.

 

Input

Output

Measurements

Note

J13 Pin #

J5 Pin #

 . .

1

31

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 0

2

32

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 1

3

33

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 2

4

34

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 3

5

35

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 4

6

36

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 5

9

37

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

LVL_1_Accept

 

B.5. Serial Clock, Data and Beam Clock test

 

Connect the pulse generator output with logic level swings to the J13 pins and monitor the bits on J5 pins as follows.

 

Input

Output

Measurements

Note

J13 Pin #

J5 Pin #

 . .

63

21

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Clock

75

24

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Latch

64

22

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Data_in

14

47

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM_38MHz

18

45

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM_9.5Mhz

Input

Output

Measurements

Note

J5 Pin #

J13 Pin #

 . .

23

71

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Ser_Data_Out_MCM

 

 

B.6. Program, Readback and Reset test

 

Connect the pulse generator output with logic level swings to the J13 pins and monitor the bits on J5 pins as follows.

 

Input

Output

Measurements

Note

J13 Pin #

J5 Pin #

 . .

76

20

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Readback

77

25

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Program_in

78

26

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM Reset

 

 

B.7. Discriminator Sum test

 

Connect a pulse generator output of 10MHz, 1.0Vp-p square pulse to the input of J5 pins and monitor the output at J13 pins as follows.

 

Input

Output

Measurements

Note

J5 Pin #

J13 Pin #

 . .

7

99

Output voltage should have the same waveform of the input

Discriminator sum output

 

B.8. Blank pins

 

These two pins, J5 -2, J5 -6, should have no connections to anywhere.

 

 

3.8 J6 connector test

 

A. Passive signal test

 

Plug in the pig-tailed connector head on the MCM side on J3. Connect the pig-tailed connector head on the Motherboard side on J13, and verify the following.

 

From

To

Measurements

Notes

J6 Pin Number

J13 Pin Number

 . .
. . . .

1

159

10k

Silicon detector bias line

3

160

short (4 ohms or less)

Silicon detector bias line return

4

128

short (4 ohms or less)

+5V analog for TGV32

5

126

short (4 ohms or less)

+5V analog return for TGV32

8, 17

94

short (4 ohms or less)

+5V analog return

9

116

short (4 ohms or less)

+5V analog for comparator

10

114

short (4 ohms or less)

+5V analog return for comparator

11

128

short (4 ohms or less)

+5V analog for AMUADC

12

126

short (4 ohms or less)

+5V analog return for AMUADC

13

134

short (4 ohms or less)

-5V analog

14

140

short (4 ohms or less)

+2.5V analog

15

148

short (4 ohms or less)

Temp sensor

19

60

short (4 ohms or less)

Serial_Enable (reset)

27

143

short (4 ohms or less)

+5V digital

28

137

short (4 ohms or less)

+5V digital return

29

139

short (4 ohms or less)

+5V digital

30, 38, 40, 42

137 or 141

short (4 ohms or less)

+5V digital return

44, 46, 48

137 or 141

short (4 ohms or less)

+5V digital return

 

 

B. Active signal tests

 

B.1. Preamp and AMUADC spy channel signal buffer tests

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J6 Pin #

J13 Pin #

 . .

16

91

Output voltage is inverted with the same amplitude as input

Preamp spy channel

18

92

Output voltage is inverted with the same amplitude as input

AMUADC spy channel

 

 

B.2. PECL clock line test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J13-13 and 15

J6 -49 and 50

Output voltage should have the same waveform of the input with approximately 4.2V for high and 3.4V for low swings

PECL clock line

 

 

 

B.3. LVDS (MCM data drive) test

 

With the same supply connections and pulse generator connections as in J1 connector tests, test the following.

 

Input

Output

Measurements

Note

J6 Pin #

J13 Pin #

 . .

39

46, 48

Output voltage should have the same waveform of the input with amplitudes of ~250mVp-p

LVDS clock +/- signal

41

49, 51

Output voltage should have the same waveform of the input with amplitudes of ~250mVp-p

LVDS data #1 +/- signal

43

50, 52

Output voltage should have the same waveform of the input with amplitudes of ~250mVp-p

LVDS data #2 +/- signal

 

B.4. Mode bit and LVL_1_Accept test

 

Connect the pulse generator output with logic level swings to the J13 pins and monitor the bits on J6 pins as follows.

 

Input

Output

Measurements

Note

J13 Pin #

J6 Pin #

 . .

1

31

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 0

2

32

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 1

3

33

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 2

4

34

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 3

5

35

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 4

6

36

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Mode bit 5

9

37

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

LVL_1_Accept

 

B.5. Serial Clock, Data and Beam Clock test

 

Connect the pulse generator output with logic level swings to the J13 pins and monitor the bits on J6 pins as follows.

 

Input

Output

Measurements

Note

J13 Pin #

J6 Pin #

 . .

63

21

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Clock

75

24

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Latch

64

22

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Data_in

14

47

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM_38MHz

18

45

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM_9.5Mhz

Input

Output

Measurements

Note

J6 Pin #

J13 Pin #

 . .

23

70

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Ser_Data_Out_MCM

 

 

B.6. Program, Readback and Reset test

 

Connect the pulse generator output with logic level swings to the J13 pins and monitor the bits on J6 pins as follows.

 

Input

Output

Measurements

Note

J13 Pin #

J6 Pin #

 . .

76

20

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Readback

77

25

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

Program_in

78

26

Output voltage should have the same waveform of the input with ACT logic output levels (0-5V)

MCM Reset

 

 

B.7. Discriminator Sum test

 

Connect a pulse generator output of 10MHz, 1.0Vp-p square pulse to the input of J6 pins and monitor the output at J13 pins as follows.

 

Input

Output

Measurements

Note

J6 Pin #

J13 Pin #

 . .

7

100

Output voltage should have the same waveform of the input

Discriminator sum output

 

B.8. Blank pins

 

These two pins, J6 -2, J6 -6, should have no connections to anywhere.