MVD mode bits

MVD mode bit definitions

Nance Ericson, Melissa Smith, and Hubert van Hecke
PHENIX-MVD-98-25, PHENIX Note 353

Below are the mode bit definitions for the MVD, as programmed into the MCM FPGA by Nance Ericson and Melissa Smith. Those functions that are common with other Phenix subsystems are assigned to the recommended standard bits, see the mode bit document.
On 31-Aug-2001, JPSullivan modified the following table. Previously, it said MB0=0, MB1=1 means integrator reset and MB0=1, MB1=0 means Resynch reset. This is wrong. MB0=1, MB1=0 means integrator reset. I am not sure that MB0=0, MB1=1 means resynch reset (I'm not even sure what resynch reset is), but I just switched them in the table below.

MB0 MB1 function
0 0 no-op
0 1 Resync Reset
1 0 Integrator Reset
1 1 Initialization Reset
.
MB3 MB2 .
0 0 no-op
0 1 Bench Calibration Enable
1 0 Phenix Calibration Enable
1 1 unassigned
.
MB4 .
0 halt
1 run
.
MB5 .
0 -
1 externally timed cal trig

previous update 17 June 98 - HvH
Last update 31 Aug 01 - JPS

MB0	MB1	function
0	0	no-op
0	1	Resync Reset
1	0	Integrator Reset
1	1	Initialization Reset
.
MB3	MB2	.
0	0	no-op
0	1	Bench Calibration Enable
1	0	Phenix Calibration Enable
1	1	unassigned
.
MB4		.
0		halt
1		run
.
MB5		.
0		-
1		externally timed cal trig