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The top plot below shows the (now solved) problem with the old ADC chip, namely that the resolution worsenes as the signals get smaller. The VCAL runs can address some of this, since we can plot the sigmas and means for our runs. This is done in the lower plot. Note that we only covered a small range in signal height. The line in the lower plot is the same as the dotted line in the top figure. Our data does not follow the line.

This picture also appears in the postscript file, pg. 18.