Strip detectors - internal alignment

In this section, we assume that the overall device has been placed exactly in its nominal position, and examine the requirements on the internal chip placement due to the so-called correlation method of vertex finding. In this method, the pattern of hits on the inner barrel can be correlated with the pattern of hits on the outer barrel: since tracks are initially almost straight, the patterns are related by a simple scale factor , where and are the radii at which the inner and outer chips are placed. The method relies on a track firing strip pairs that obey this scaling rule.

Some chip placement aberrations result in a track ending up in a strip neighboring the expected one, reducing the peak value of the correlation function. Preventing this kind of error defines most of the constraints on placement of the chips in 3 directions, z (along the beam axis), R (radial), and s (circumferential, or R*d), plus the 3 rotations around these axes. The chips lie at radii and , which are 5 and 8.0 cm, respectively. The size of a chip in the z-direction () is taken to be 5.3 cm, and the detector ``cylinders'' have a hexagonal cross-section.

The correlation method is only concerned with the relative placement of chip pairs, one chip on the inner cylinder and the corresponding chip(s) on the outer cylinder. Here, one example of the determination of the alignment constraints is given. The other constraints are determined similarly and are summarized in table 1.

Consider the displacement in R () of one of the cylinders relative to the other. When scaling the outer pattern by the nominal , a radial displacement would result in a pattern that is improperly scaled. A calibration procedure could find the actual , but the nominal ratio will presumably be a ratio of integers, potentially hard-wired in a fast vertex finder. In order to limit the error such that in the worst case, a track is displaced by 1 strip (200m),

This is satisfied if radial displacement of the outer chip is less than 0.4mm.

 
Table 1: Summary of tolerances in placement of inner/outer chip pairs relative to each other from correlation method

These tolerances, summarized in table 1, are between inner/outer chip pairs only. Suppose that a chip pair is joined such that they meet these tolerances. There are further constraints on the positions of chips pairs relative to the beam. Again, consider one example. There is a constraint in R, which leads to a limit of:

The pair must be placed at a radial distance which is known better than 0.8mm. This should be compared to the size of the Au+Au beam in the transverse direction, 0.45mm. Table 2 summarizes the constraints on the positions of pairs of chips relative to the beam. These constraints are not as stringent as those on the relative positions of the chips.

 
Table 2: Summary of tolerances on the placement of chip pairs relative to the beam from correlation method, where each pair of chips are positioned relative to each other within the tolerances given in table 1.

The correlation method of vertex finding leads to the limits given in tables 1 and 2. The pseudo-tracking method combines a hit on any of the inside chips with a hit on any of the outer chips, which may pose limits on the relative placement of all chips simultaneously, not just in pairs. In order for this method to work, all pairs must be able to point to the same vertex. This implies relative placement requirements between any pairs of chips similar to those in table 1. However, this is an offline method, and the positions of chips may be calibrated using tracks reconstructed from other detectors. Such calibrations would work for all aberrations except rotations around r and z. However the tolerances imposed on these angular placements by the correlation method are much more stringent than anything needed to define a vertex to 1mm. Thus the pseudo-tracking method imposes no further restrictions.