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Introduction

In this note, we present tests on the BVXIII chip. Preliminary test results were described in the Phenix note "Research Progress on the PHENIX Silicon Vertex Detector" dated August 24, 1992. In the Fall of 1992, we realized that an incorrect resisitor had been installed on the hybrid circuit board leading to smaller noise measurements than had been observed by Oak Ridge. Due to capacitive coupling problems with our charge injection method, the influence of the lower valued resisitor was masked in several measurements. We corrected these discrepancies and repeated our tests on the BVXIII chip.

A BVXIII chip was tested at Los Alamos National Laboratory in a clean tent with a Alessi RHM-06 probe station. Measurements were taken with a Tektronix Digitizing Signal Analyzer (DSA) allowing a direct study of the silicon signals. A Tektronix P6201 x1 FET probe was attached to a micromanipulator which measures the high impedance and low capacitance signals of the chip. The chip was mounted on and wirebonded to a ceramic hybrid circuit board constructed at LANL. The hybrid board is made of 0.63mm alumina and the design is shown in figure 2. Alumina was chosen as the hybrid material because it has the same thermal properties as silicon.

2 Measurements

We measured the amplitude of the output signal, peaking time, and gain on six channels of the chip. In order to mimic a minimum ionizing particle, we injected 4fC of charge into the channels; this corresponded to a 0.8mV transition into a 5pF capacitor. The peaking time adjust was set to +2.0V corresponding to the recommended peaking time of approximately 200 nsec on channel 3. The results are shown in Table 1 and are comparable to Fermilab measurements [2]. A sample signal response from channel 1 is shown in Figure 3. There is little variation in response from one channel to the next. The average gain measured over all six channels is 83.9mV/fC.

The sensitivity of the peak time and gain to the peaking time adjust was measured on a single channel of the chip. The results are shown in Table 2. We found that the gain and peaking time are very sensitive to the peaking time adjust which varies chip to chip.

The dynamic range of the chip was measured by varying the amount of charge injected into a channel. The peaking time adjust is set at 2.0 V. The results are shown in Table 3. The negative polarity signal saturates more quickly than the positive input signal.

Equivalent noise charge (ENC) measurements were also performed. The ENC can be calculated as follows:

where the RMS_(noise) is the root mean square of the noise distribution, calculated by the Tektronix DSA and G is the gain measured from the output pulse response. Noise measurements on channel 5 are shown in Table 4 with a variable peaking time adjust (PKA) to yield a peaking time of 200ns. Although reasonable, the noise measurements and resulting slope are larger than what was measured in the tests conducted at Fermilab. Measurements indicate that we still have problems with shielding our detector and electronics properly. We are looking into acquiring proper RF shielding which will further minimize the noise detected in our measurements.

3 Summary

Figure 1: BVXIII Chip Design

Figure 2: Hybrid Design

Figure 3: Typical output pulse from channel 1 upon injection of 4fC into the chip preamp

4 Acknowedgements

5 REFERENCES AND NOTES

1. Britton, C. Schematic of the N15 BVXIII Chip, Oak Ridge National Laboratory, Instrumentation and Controls Division. May 1,1991.
2. Zimmerman, T. "Performance of a New Monolithic Eight Channel Charge Sensitive Preamplifier-Shaper." Fermilab, unpublished, August, 1991.