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| bits | name/purpose | working? (yes/no) | notes
| 1-4
| level-1 delay
| yes
| level-1 delay adjust from 32 to 47 clock ticks.
| 5-8
| not used
| n.a.
| n.a.
| 9
| "test count mode enable"
| yes
| when this bit is set to 1,
all data packets contain data values of 1, 2, 3, ...
Setting it to zero turns this test mode off. This was tested and
found to work correctly 17-Feb-1999.
| 10
| IREN
| yes
| Used to enable internal resets. When turned
on (=1) a preamp reset signal (PRE_RST = pin 138 out from heap
manager) will be sent out at a frequency controlled by the IR0 and
IR1 bits. This is intended for various test modes, since these
resets will be sent to the MCM's externally in real phenix
running conditions. For testing the MCM without the master phenix
timing system, this is turned on (bit set to 1). On March
18, 1999 using mcm7.hex, this was working.
| 11
| SLCT1
| yes
| along with SLCT0, this is used to decide how many bits
the ADCs use. This was tested February 17, 1999. Setting SLCT1=0 results
in a 0 Volt output level at pin 173 of the heap manager. Setting SLCT1=1
results in a 3.67 Volt output level at pin 173. So, this bit seems to work.
| 12
| SLCT0
| yes
| along with SLCT1, this is used to decide how many bits
the ADCs use. This was tested February 17, 1999. Setting SLCT0=0 results
in a 0 Volt output level at pin 185 of the heap manager. Setting SLCT0=1
results in a 3.66 Volt output level at pin 185. So, this bit seems to work.
| 11-12
| SLCT1/0
| yes
| I can also test the combination of these two bits. These control
the number of bits used by the ADC. This, in turn, changes the length of the
CLK_EN signal which comes out of the heap manager at pin 49. The details
are given in
this note. For 9 bits, the signal should be about 6.4 microsec.
10 bits should give 12.8 microseconds, 11 bits 25.6 microsec, and 12 bits
51.2 microsec. This calculation assumes the 4X clock runs at 40 MHz (or
beam clock is 10 mHz). However, these is a timeout feature in the heap
manager software which does not allow it to count above 1600. Therefore,
the width of CLK_EN should be about 20 microsec.
I can test this:
| SLCT0=1, SLCT1=1, which gives 9 bits, should see 6.4 microsec width, actually see 6.4 microsec. SLCT0=0, SLCT1=1, which gives 10 bits, should see 12.8 microsec, actually see 12.6 microsec. SLCT0=1, SLCT1=0, which gives 11 bits, should see 20 microsec, actually see 19.5 microsec. SLCT0=0, SLCT1=0, which gives 12 bits, should see 20 microsec, actually see 19.5 In summary, this works. 13
| RAW_MODE
| yes
| Used to decide whether the mcm should send out
one packet per level-1 trigger (post-pre) or two (both pre and post
samples). This must be consistent with the setting of CORR_SEL in
the AMU/ADC part of the serial string. In this case, consistent means
the bit setting must be opposite. When RAW_MODE=0, the system sends out
one packet per level on trigger. When RAW_MODE=1, there are two packets
per level 1. This was tested and seemed to work on February 17, 1999.
| 14
| CAL_EN
| yes
| normally this bit is 0. When set to 1, the
calibration mode is enabled. This is used to injected
into the preamps for testing and calibration. The charge is actually
injected only when you
| 1) pulse "Ben Cal Enable" 2) there is a preamp reset. The actual charge injection is triggered by a preamp reset -- which can come from either setting IREN=1 (causing regular, automatic preamp resets) or it can be triggered externally via Mode bit 0. The magnitude of the charge injected is controlled by the VCAL_DAC in the TGV serial string. One way to check this is to look for an output on CAL_DIS (pin 4) out of the heap manager. 15
| IR1
| yes
| along with IR0, this bit controls the preamp reset
frequency. IREN turns this internal reset on/off. These bits
control the frequency. This was working, 18-Mar-1999
with mcm7.hex.
| 16
| IR0
| yes
| along with IR1, this bit control the preamp reset
frequency. IREN turns this internal reset on/off. These bits control
the frequency. This was working, 18-Mar-1999 with mcm7.hex.
| |