PHENIX Muon Identifier FEE Specifications

K. Read

Oak Ridge National Laboratory (ORNL), Oak Ridge, TN 37831, USA

(phenix-muon-95-18; submitted: 26 September 1995; revised 31 October 1995; revised 1 August 1996)

Assumption

There could be significant sources of electronic noise at RHIC. At the time of this writing it is not known that an acceptable S/N can be achieved for readout of eight 5.5-m long wires ganged passively and read out from the far end of a 7-m micro-coax cable. Therefore, the following presumes a readout scheme with an inexpensive active filter/driver located on each "external connector." This is a custom connector card which plugs into the endcap on one end of each Iarocci tube. The external connector will have a decoupling capacitor, an off-the-shelf filter/driver, and connections to one pair of a 7-m long, twisted pair, flat cable for the output.

Specifications

The following are preliminary specifications for the front-end electronics for the Muon Identifier, with the above mentioned assumptions about the requirement for a filter/driver:

Pre-preamp
- off-the-shelf active driver/filter (may be needed) at tube endcap
- drives 7-m twisted pair
- modest power dissipation
- extremely reliable due to minimal access
Front end amplifier
- design for negative going signals (read out of eight ganged Iarocci tube wires)
- 8-channel chip implementation
- 0.5 pC most probable pulse
- most pulses are within three times mean but a non-negligible fraction will have maximum pulse of 20-100 times the mean
- 8 bits dynamic range
- design for 7-m cable between Iarocci tube and motherboard (twisted pair if pre-preamp used, otherwise 50 ohm micro-coax [RG-174])
- 5 ns rise time
- 40 ns drift time interval
- allow this preamp version to also be used for the muon tracker CSC anode wires if possible
- non-radiation hardened technology
- need calibration circuit and mask register
- 8928 channels
Post amplifier
- leading edge discriminator with adjustable threshold to provide fast trigger on preamp output current pulse; 10 mV minimum threshold; (2 V maximum threshold)
- re-use existing PHENIX AMU/ADC with minimal development
- 8 bit AMU/channel; pre and post samples; 64 cells deep
- 8 bit ADC/channel
General
- diode protection on all inputs
- total power < 200 mW/channel
- fiber optic connections for all signals in or out of motherboard
- one motherboard per muID panel; 48 panels; 48 motherboards
- 136, 176, or 216 channels per motherboard depending on panel
- one heap manager per motherboard
- must be able to perform local LVL-1 trigger logic

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Last version: August 1, 1996