Design Criteria for Muon Tracking Electronics

Design Criteria for the Muon Tracker Electronics

D. M. Lee and W. Sondheim

Los Alamos National Laboratory

(PHENIX-Muon-95-17); submitted: September 14, 1995

Subject: Summary of Decisions from 9/5/95 FEE Meeting at ORNL

A meeting was held at ORNL to discuss the front end electronics for the Muon Tracker. The attendees were Ken Read, Ed Kennedy, John Halliwell, Alan Wintenberg, Hee Kim, Glenn Young, Dave Lee, and Walt Sondheim. The purpose was to review the Muon tracker electronics needs and attempt to arrive at a set of criteria so that the design work can begin. The following is a summary of the results of that meeting.

Front end Amplifier - High resolution cathode

A shaping amplifier will be implemented with a integration time of 500 ns and a decay time of less than 10 us. The choice of shaping method will be left to the designer, Ed Kennedy. The following characteristics will be incorpoated into the design,

Amplifier power < 50 mWatts/channel.
8 channel chip implementation
80 femtocoulomb, most probable pulse
800 femtocoulomb, maximum pulse
Calibration capacitors incorporated into chip on each channel
Calibration capacitors matched to better than 1% of their value
Calibration will be all even channels on one pin and all odd on another pin
12 bits dynamic range, 1 bit noise = < 1% of most probable pulse.
Design for 20 cm input cable via twisted pair.
non rad hard technology.
design for positve signals
channel to channel the same to 1% on each plane.

Post Amplifier - High Resolution Cathode

The electronics implementation after the front end amplifier up to but not including the DCM has the following criteria,

Multiple samples( up to 5) desired - 11-12 bit AMU/channel required, 12 bit desired.
11-12 bit ADC/channel required,12 bit desired.
total power < 200 mWatts/channel
fiber optic connections for all signals in or out of mother board deemed veryimportant.
copper conductors for DC power and grounds and HV.
One calibration DAC per motherboard, 8 bits.
Heap manager to service 128 channels or less ( 16 bits x 128/40 us = 50 Mb/s)
Heap manager segmentation by plane not by phi

Coarse Cathode

The coarse cathode requires a latched output with the following criteria,

Utilize the high resolution cathode front end amplifier.
Implement a comparator for the latch. Ed Kenndy will design ( a suggestion was made to implement the comparator into the 8 channel front end chip - desireable but no decision made.)
Calibration scheme same as high resolution cathode
One adjustable threshold per motherboard/plane.
Signal levels same as high resolution cathode.
12/1 signal to noise.
20 cm input twisted pair cable.
post FEE electronics to be in common with other phenix system. LUND chip o.k.
fiber optic input and outputs deemed very important, DC power and HV on copper.
Heap manager segmentation by plane not by phi.

Anode

The anode requirements are the same as the coarse cathode with the following exceptions,

design for negative going signals
use amp/latch design of MUID if possible.
amplifiers will be located along the chamber frame.
anode wires may be ganged up to 4 channels.

General

General specifications are,

inputs for all channels will be via 34 pin IDC connector, 16 channels per connector with grounds carried thru.
clear unobstructed view path at top of octants in station 2 of 5 cm square will be provided. The locations are in the center of the octant, and approximately 50 cm from the edge.
motherboards will be common to all three stations.
heap managers can be off the mother board.
heap managers can service more than one mother board.
Diode protection on all inputs
All grounds are independent of magnet.

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