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Electronics Requirements for the CSC Chambers

D. M. Lee
Los Alamos National Laboratory, Los Alamos, NM 87545
(phenix-muon-95-13; submitted: 10 August 1995; Revised: 16 August 1995)

Introduction

The muon tracker has approximately 16000 channels of electronics on the high resolution cathodes, 8000 channels of electronics on the anodes, and 8000 channels of electronics on the low resolution (coarse) cathodes. The three coordinate readout on each cathode strip detector allows for space point reconstruction on each detector without the requirement of using additional detectors to resolve ghost hits. The anode and low resolution cathode electronics requirements are somewhat straight forward because no amplitude or timing information is required. The high resolution cathode however has somewhat more stringent requirements because the resolution achievable depends on the noise levels and the linearity of each channel. The following is a discussion of the electronics requirements imposed on the front end electronics to achieve the desired performance of the muon tracking system.

Characteristic Counting Rates and Times

To properly design the front end electronics an understanding of the strip counting rates is needed. The updated CDR lists the following parameters:

beam conditionInteraction Rate dN/detatime
p + p454 kHz2.62.2us
Au + Au (MB)13.9 kHz21072.2us
Au + Au (Cn) 1.4 kHz878721.6us

The multiplicity's quoted are from the target. M.L.Brooks has determined through simulations that the multiplicity's in the muon tracker are 50 for Au + Au (Cn) events. This means that only .045 of all tracks enter the tracker. This reduction factor could be applied to the MB events for Au + Au or p + p. The occupancies for each strip can be determined in the following manner,

Readout pitch= 1 cm
number of readouts= 6.28*R,R = outer radius of station
occupancy= 3x (50/6.28*R)

where 3x includes charge sharing on more than one strip.

Therefore, for station 1 the strip occupancy is,

Au + Au (Cn) occupancy= 0.17 counts/strip/crossing event
Au + Au (MB) occupancy= 0.04 counts/strip/crossing event

The occupancy per strip is therefore quite low ( a few percent). The ability of the detector design to resolve all ghost hits allows us also to always know that a multiple track on the high resolution cathode has occurred. If we know that a multiple track has occurred then resolving the two tracks is possible. The only requirement is that the charge from both tracks is integrated correctly. This requirement implies that the integration time of the front end amplifier should be much longer than the drift time in the chamber gas so that variations in charge integration between the two tracks is minimized. Integration times of up to 500 ns are therefore desirable.

Another important parameter is the length of time available on average before unacceptable pileup occurs. For an integrate and reset front end pileup can naturally occur and subtraction of two samples is necessary. If a front end shaper is used then the signal decay time can be adjusted to decay to a prescribed level so the probability of pileup is small. The average count rate is calculated as follows,

Au + Au (Cn)= 0.17 x 1.4 kHz= 240 counts/s
Au + Au (MB)= 0.04 x 13.9 kHz= 600 counts/s
Total= 840 counts/s
Given a strip rate of 840 counts/s, the probability of 2 events occurring in 100 us is .003, very small. Therefore, a pulse with a long tail can persist for 100 us. The decay time allowed for a pulse to decay to less than 1 bit out of 12 bits is 12us. The specification for signal processing using a shaper is that the rise time should be greater than 500 ns and the decay time should be less than 12 us.

CSC Detector Characteristics

The high resolution cathodes have .5 cm wide strips and a readout pitch at 1 cm, i.e. every other cathode is readout. The intermediate cathode signal is capacitively coupled to the readout strips and the intermediate cathode will have a large value resistor of approximately 1 megohm to ground to prevent the strip from floating up to high voltage. The cathode strip will be either gold or aluminum with a resistance of approximately 1 ohm per square. The capacitance of the strip is dominated by the interstrip capacitance and is approximately 1.3 pf/cm. The amplifier will see two capacitances in series and so will see one half of 1.3 pf/cm or .65 pf/cm. For chambers 3 meters long the maximum capacitance for the front end electronics is 150 pf. Since the strips on all stations will be variable in length the front end capacitance will vary from 0 to 150pf. The high resolution cathodes will be DC coupled into the amplifiers.

The low resolution cathodes will be 1 cm strips and readout at a 2 cm pitch. The strip resistance and capacitance will be 1 ohm per square and .65 pf/cm respectively. The strip capacitance will vary from 0 to 150 pf. The low resolution cathode will be DC coupled into the amplifiers.

The anodes are spaced at 1 cm and will be read out at 1 or 2 cm intervals depending on the occupancy. The anodes will be at high voltage, 2500 volts, and therefore the anode signals will be AC coupled to the amplifier via a 100 pf capacitor. We expect to use a fast gas and have a maximum drift time in the gas to the anode of about 50 ns.

The Detector signals.

The charge on the anode is due to ionization in the gas caused by passage of the muon through the gas volume and the gain of the chambers. In a typical gas volume the ionization process produces about 140 electrons/cm so in the CSC chambers the number of electrons produced will be 140 x .7 cm electrons or 100 electrons per track. Assuming a gain in the chamber of 2 x 10**4 , the anode charge will be 2 x 10**6 electrons. The cathode charge is one half of the anode charge times a reduction factor called the "ballistic deficit factor" that is due to the finite integration times. Taking a ballistic deficit factor of .5 the total cathode charge will be 5 x 10**5 electrons or 80 fC. The front end electronics on the high resolution cathode should be designed for 80 fC or less input signal and must have a noise level of .8 fC or less for us to achieve a resolution of 100 microns. This is the typical 1% noise level restriction.

Dynamic Range

The dynamic range of the high resolution cathode electronics depends on the signal to noise level , energy loss fluctuations, and a margin of error required to take into account the variations in the gain of the front end amplifiers and the following AMUs. The dynamic range is calculated as follows,

x 100signal to noise
x 10energy loss fluctuations
x 2margin
2000minimum needed dynamic range or 11 bits

A prudent design of 12 bits would be desirable for the dynamic range of the amplifier .

The FEE Scheme

The front end electronics can be designed to be one of the following:
  1. Integrate and reset method similar to that employed by the MVD

  2. An amplifier and shaper with no need for reset
Method 1 requires a presample to be subtracted from the signal level of interest to get the corrected signal . This subtraction automatically introduces a factor of 1.4 increase in the noise contribution to the signal. For a high resolution system this is undesirable. Additionally, previous experience with a similarly designed integrator( SVX-H) has shown that bad channels that have unreasonably high leakage currents for whatever reason adversely effect adjacent channels by saturating the bad channel and feeding additional leakage currents to the next nearest channels. The longer the integration time the larger the number of effected channels.

Method 2 requires no presample subtraction except for a pedestal subtraction which can be accurately determined at a calibration time and subsequently stored in a computer.

The preferred FEE scheme is Method 2 because of a better noise level, no reset transients, no saturated channels to interfere with adjacent channels, and the baseline is more solid.

Low Resolution Anode and Cathode FEE

The signal to noise requirement for the anode and cathode front ends are simply that the noise level should be low enough so that at a thresold adjusted to give > 99% efficiency, the noise contribution to the strip or wire singles rate should not be significantly greater than the singles rate with beam. The threshold should be a factor of three below the most probable signal. The threshold to noise is determined from the following:

                  

where V_t is the voltage threshold, is the noise level, f_n is the noise frequency, and tau is the amplifier time constant. For a time constant of 500 ns and a noise frequency of 85 counts/sec, the threshold to noise should be 4/1. If the signal to threshold is 3/1 than the signal to noise should be 12/1.

The CSC anode front end can be identical to the front end being designed for the Muon ID. The Cathode FEE is similar to the anode except the polarity is for positve signals and the amplitude is between .25 and .5 of the anode.