All pictures in the SVX images directory
link to older / obsolete pictures
282 -18 how to add your pictures
Pictures found: 264
Dave
Dave
Total today: 264 pictures
Script last updated 21 June 2007
by Hubert van Hecke
|
All pictures in the SVX images directory link to older / obsolete pictures 282 -18 how to add your pictures Pictures found: 264 | |||
| | FVTX Preliminary Drawing Package.pdf | ||
| | FVTX_8-10-2007.easm | ||
| | PhenixCentralUpgradeAssy6.pdf | ||
| | VTX Top Assembly-1 06-21-07.jpg | ||
| | VTX Top Assembly-2 06-21-07.jpg | ||
| | dr_lay2_sensor8x_72.ps | ||
| | raa_redbars.xcf | ||
| | stat_sys_withfvtx.png | ||
| | svtx top assembly 2.jpg | ||
| | svtx_assy_2-06c.gif | ||
| | svtx_barrel_half_assy_5-11-07.jpg | ||
| | wedge-A-sheet-B6.png | ||
| | FVTXHalfAssy1.pdf | ||
| | FVTX_Detector_Module_low_assembled_2-29-08.jpg | ||
| | FVTX_Disk_Detector_Assy_front_1.jpg | ||
| | FVTX_Half_Assy_3.jpg | ||
| | FVTX_ReadoutCardOutline_4-25-08.png | ||
| | PhenixCentralUpgradeAssy4.pdf | ||
| | PhenixCentralUpgradeAssy5.pdf | ||
| | PhenixCentralUpgradeAssy6.jpg | ||
| | RSmith7-20-06.png | ||
| | Sensor-size.gif | Attached is a picture of the sensor and wedge sizes for the FVTX
disks. Each sensor has 7 chips. The strip pitch is 75 microns with a 0.5
mm dead area on the edge of the chip and 0.5 mm overlap.
Dave | |
| | VTX-FVTX-boundary111-PHX-01-1002.png | ||
| | bigwheel seal 6-21-07.jpg | ||
| | control_drawing.gif | ||
| | dmu_big_dca_straight.png | ||
| | dmu_big_dca_straight.xcf | ||
| | dmu_bmu_p_sigtobackground_2.xcf | ||
| | fifo_array.jpg | ||
| | hirose_df30_series.pdf | ||
| | moss_bgd.gif | ||
| | phenix_big_sideview.png | ||
| | sensor_wedge_B2_1-5-07.pdf | ||
| | si_endcap_rear_ckt_board_assy3.gif | ||
| | svtx_assy_3-06.gif | ||
| | svtx_assy_spiro_layout_11-05.gif | ||
| | svtx_top_assembly_2.jpg | ||
| | svtx_update_2-06.ppt | ||
| | wedge-A-sheet-B4.pdf | ||
| | wedge-A-sheet-B5.png | ||
| | wedge-B-sheet-B1.png | ||
| | wedge-B-sheet-B2.pdf | ||
| | wedge-B-sheet-B3.pdf | ||
| | wedge-B-sheet-B3.png | ||
| | BJpsi.png | ||
| | BJpsi.xcf | ||
| | D2290703_PHENIX.jpg | ||
| | FVTXHalfAssy4.jpg | ||
| | FVTXHalfAssy4.pdf | ||
| | FVTX_Detector_Module_assembled_2-29-08.jpg | ||
| | FVTX_Detector_Module_back-side_assm_2-29-08.jpg | ||
| | FVTX_Detector_Module_backside_connector_end_assm_2-29-08.jpg | ||
| | FVTX_Detector_Module_exploded_2-29-08.jpg | ||
| | FVTX_Detector_Module_front-side_high_assm_2-29-08.jpg | ||
| | FVTX_Detector_Module_large_backside_explode_2-29-08.jpg | ||
| | FVTX_Half_Disk_4-wedges_assm_2_2-29-08.jpg | ||
| | FVTX_Half_Disk_explode2_2-29-08.jpg | ||
| | FVTX_Half_Disk_no_ext_cables_assm 2_2-29-08.jpg | ||
| | FVTX_ReadoutCardOutline_4-25-08.pdf | ||
| | FVTX_sensor_wedge.png | ||
| | HDI_assy_drawing_1.png | ||
| | HDI_assy_drawing_2.png | ||
| | HDI_assy_drawing_3.png | ||
| | Phenix Central Upgrade Assy 1.pdf | ||
| | PhenixCentralUpgradeAssy4.jpg | ||
| | PhenixCentralUpgradeAssy5.jpg | ||
| | VTX.jpg | ||
| | VTX_Top_Assembly_7_9-06.jpg | ||
| | barrel_acc_04jan06.png | ||
| | before_after_mass2.png | ||
| | chi2_3gev.png | ||
| | chi2_3gev.xcf | ||
| | chip_trace.png | ||
| | dmu_big_straight.png | there is an xcf (gimp) file with elements in separate layers | |
| | dmu_bmu_mi_sigtobackground.png | ||
| | dmu_bmu_n_sigtobackground_2.png | This xcf file (Gimp native format) was used to make the png file of the same name. Typically the xcf file contains layers with separate info. In this case, there is the original plot containing just the dots, a separate layer for the lines connecting the dots, one layer for the legend. So if for example you want this plot without the lines, pick up this xcf file and use Gimp to turn off the layers you don't want. | |
| | dmu_bmu_n_sigtobackground_2.xcf | This xcf file (Gimp native format) was used to make the png file of the same name. Typically the xcf file contains layers with separate info. In this case, there is the original plot containing just the dots, a separate layer for the lines connecting the dots, one layer for the legend. So if for example you want this plot without the lines, pick up this xcf file and use Gimp to turn off the layers you don't want. | |
| | dmu_bmu_p_sigtobackground_2.png | ||
| | dmu_bmu_sigtobackground.png | ||
| | dr_lay1_sensor8x_71.ps | ||
| | fvtx_cage_1_apr08.png | ||
| | fvtx_cage_2_apr08.png | ||
| | fvtx_cage_3_apr08.png | ||
| | fvtx_cage_4_apr08.png | ||
| | fvtx_cage_5_apr08.png | ||
| | fvtx_cage_drawings_3-28-08.pdf | ||
| | neg_muon_sources.png | ||
| | neg_muon_sources.xcf | ||
| | pikdb_dcas.png | ||
| | pixel_block_diagram.jpg | ||
| | pt-mu-relative-hadron-both-noPIDcuts.png | ||
| | pulser.jpg | ||
| | raa_theory_MD_IVAN_both.xcf | ||
| | raa_theory_MD_IVAN_ldrd.png | ||
| | raa_theory_MD_IVAN_proposal.png | ||
| | sensor_wedge_B1_1-5-07.pdf | ||
| | si_endcap_rear_ckt_board_assy3_dwg.gif | ||
| | si_tower_assy4a_3-7-06.gif | ||
| | signal_back.png | ||
| | sil_endcap_half_assy_3-06.gif | ||
| | sil_endcap_half_assy_detail_3-06.gif | ||
| | svtx top assembly2.jpg | ||
| | svtx top assembly2b.jpg | ||
| | svtx_FVTX_exploded.jpg | ||
| | svtx_Top_Assembly_with_iFVTX_1.jpg | Here are a couple of pictures that Roger Smith and I put together, for Sergey, to use in his IEEE presentation. These pictures show the four planes of the iFVTX detector located at the same Z locations as the planes for the FVTX array. Each of the three larger planes consists of two 8 X 11 FNAL sensor planes, mounted to a piece of TPG, set into a "window pane" board. The sensor arrays in each plane face each other with a 6. mm gap between the face of the backing boards. The first plane has a sensor array that is 8 X 4. One piece of information that would be very useful to understand the Z space required - would be the dimensional specifications for the connectors that will be mounted to the outside face of the backing or support boards, and how many will be needed. Cheers, Walt | |
| | svtx_assy_section_noFVTX_isometric11-05.gif | ||
| | svtx_assy_section_no_FVTX_11-05.gif | ||
| | svtx_assy_vtx_cables_11-05.gif | ||
| | thumbnail.py | ||
| | wedge-A-sheet-B4.png | ||
| | wedge-A-sheet-B5.pdf | ||
| | wedge-A-sheet-B6.pdf | ||
| | wedge-B-sheet-B1.pdf | ||
| | wedge-B-sheet-B2.png | ||
| | |||
| | test: | ||
| | D2290703_PHENIX.jpg | ||
| | FVTX_Disk_2_half_assy1.jpg | ||
| | FVTX_Disk_2_half_assy2.jpg | Roger and I have taken a first pass at trying to layout the HDI and wiring from the FVTX large disks in a way that provides reasonable clearances to mounting tabs and cooling tubes. The result is an HDI outline that features a narrow "tail" at the OD, with two of the 100-pin connectors for the extension cables. These tails would be bent at 90 degrees toward the magnet poles. The same exact HDI can be used on all wedges, but the tail is bent to one side or the other, depending on the side of the disk that particular wedge is mounted to (if the HDI are manufactured with a built-in bend, two different variants will be needed). Please refer to the attached drawing (pdf) for details. Also, look at the images below for a better idea of how this packages together. The HDI also feature two pin holes for alignment to the back-plane (and ultimately the Silicon detector), and three through holes for screws that would hold the wedges onto the support panels. Note that there is some flexibility in the position of the screw and pin holes. I would appreciate feedback about this configuration. Please note that we are using this configuration to define the locations of the mounting tabs in the support cage. This impacts the iFVTX group, as we are in the process of defining the envelope and mounting hole locations on their boards (i.e. please send me feedback sooner rather than later). Thanks! Eric HYTEC | |
| | FVTX_Disk_Detector_Assy_front_1.jpg | ||
| | FVTX_Half_Assy_3.jpg | ||
| | FVTX_Half_Assy_4.jpg | ||
| | FVTX_Half_Assy_5.jpg | ||
| | VTX Top Assembly-1 06-21-07.jpg | ||
| | VTX Top Assembly-2 06-21-07.jpg | ||
| | VTX.jpg | ||
| | VTX_Top_Assembly_7_9-06.jpg | ||
| | bigwheel seal 6-21-07.jpg | ||
| | dmu_big_dca_straight.png | ||
| | dmu_big_dca_straight.xcf | ||
| | dmu_big_straight.png | there is an xcf (gimp) file with elements in separate layers | |
| | dmu_bmu_mi_sigtobackground.png | ||
| | dmu_bmu_n_sigtobackground_2.png | This xcf file (Gimp native format) was used to make the png file of the same name. Typically the xcf file contains layers with separate info. In this case, there is the original plot containing just the dots, a separate layer for the lines connecting the dots, one layer for the legend. So if for example you want this plot without the lines, pick up this xcf file and use Gimp to turn off the layers you don't want. | |
| | dmu_bmu_n_sigtobackground_2.xcf | This xcf file (Gimp native format) was used to make the png file of the same name. Typically the xcf file contains layers with separate info. In this case, there is the original plot containing just the dots, a separate layer for the lines connecting the dots, one layer for the legend. So if for example you want this plot without the lines, pick up this xcf file and use Gimp to turn off the layers you don't want. | |
| | dmu_bmu_p_sigtobackground_2.png | ||
| | dmu_bmu_p_sigtobackground_2.xcf | ||
| | dmu_bmu_sigtobackground.png | ||
| | dr_lay1_sensor8x8_assy.gif | ||
| | dr_lay1_sensor8x_71.ps | ||
| | dr_lay2_sensor8x12_assy.gif | ||
| | dr_lay2_sensor8x_72.ps | ||
| | fifo_array.jpg | ||
| | iFVTX_Assembly_3.jpg | ||
| | phenix_simple_sideview.jpg | ||
| | phenix_simplified_assy2.jpg | ||
| | pixel_block_diagram.jpg | ||
| | pulser.jpg | ||
| | svtx top assembly 2.jpg | ||
| | svtx top assembly2.jpg | ||
| | svtx top assembly2b.jpg | ||
| | svtx_FVTX_exploded.jpg | ||
| | svtx_Top_Assembly_with_iFVTX_1.jpg | Here are a couple of pictures that Roger Smith and I put together, for Sergey, to use in his IEEE presentation. These pictures show the four planes of the iFVTX detector located at the same Z locations as the planes for the FVTX array. Each of the three larger planes consists of two 8 X 11 FNAL sensor planes, mounted to a piece of TPG, set into a "window pane" board. The sensor arrays in each plane face each other with a 6. mm gap between the face of the backing boards. The first plane has a sensor array that is 8 X 4. One piece of information that would be very useful to understand the Z space required - would be the dimensional specifications for the connectors that will be mounted to the outside face of the backing or support boards, and how many will be needed. Cheers, Walt | |
| | svtx_barrel_half_assy_5-11-07.jpg | ||
| | svtx_top_assembly_2.jpg | ||
| | thumbnail.py | ||
| | |||
| | backup: | ||
| | BJpsi.png | ||
| | BJpsi.xcf | ||
| | D2290703_PHENIX.jpg | ||
| | FVTX_Disk_2_half_assy1.jpg | ||
| | FVTX_Disk_2_half_assy2.jpg | Roger and I have taken a first pass at trying to layout the HDI and wiring from the FVTX large disks in a way that provides reasonable clearances to mounting tabs and cooling tubes. The result is an HDI outline that features a narrow "tail" at the OD, with two of the 100-pin connectors for the extension cables. These tails would be bent at 90 degrees toward the magnet poles. The same exact HDI can be used on all wedges, but the tail is bent to one side or the other, depending on the side of the disk that particular wedge is mounted to (if the HDI are manufactured with a built-in bend, two different variants will be needed). Please refer to the attached drawing (pdf) for details. Also, look at the images below for a better idea of how this packages together. The HDI also feature two pin holes for alignment to the back-plane (and ultimately the Silicon detector), and three through holes for screws that would hold the wedges onto the support panels. Note that there is some flexibility in the position of the screw and pin holes. I would appreciate feedback about this configuration. Please note that we are using this configuration to define the locations of the mounting tabs in the support cage. This impacts the iFVTX group, as we are in the process of defining the envelope and mounting hole locations on their boards (i.e. please send me feedback sooner rather than later). Thanks! Eric HYTEC | |
| | FVTX_Disk_Detector_Assy_front_1.jpg | ||
| | FVTX_Half_Assy_3.jpg | ||
| | FVTX_Half_Assy_4.jpg | ||
| | FVTX_Half_Assy_5.jpg | ||
| | FVTX_sensor_wedge.png | ||
| | FVTX_space11.png | Dear Dave and Melynda, Roger Smith has generated the attached drawing to show the space Between the VTX barrel layers and the FVTX cage and sensors. This picture incorporates the longer pixel ladder design as shown in Yasiyuki's first picture attached in his e-mail of this morning; namely the mounting block at layer 2 is outside the 20 degree acceptance line. This view also shows the previous design for the FVTX - nothing has been changed. Cheers, walt | |
| | FVTX_space_4-18-07.png | ||
| | FVTX_space_4-18-07.xcf | ||
| | RSmith7-20-06.png | ||
| | Sensor-size.gif | Attached is a picture of the sensor and wedge sizes for the FVTX
disks. Each sensor has 7 chips. The strip pitch is 75 microns with a 0.5
mm dead area on the edge of the chip and 0.5 mm overlap.
Dave | |
| | VTX Top Assembly-1 06-21-07.jpg | ||
| | VTX Top Assembly-2 06-21-07.jpg | ||
| | VTX-FVTX-boundary111-PHX-01-1002.png | ||
| | VTX.jpg | ||
| | VTX_Top_Assembly_7_9-06.jpg | ||
| | barrel_acc_04jan06.png | ||
| | before_after_mass2.png | ||
| | bigwheel seal 6-21-07.jpg | ||
| | chi2_3gev.png | ||
| | chi2_3gev.xcf | ||
| | chip_trace.png | ||
| | control_drawing.gif | ||
| | dmu_big_dca_straight.png | ||
| | dmu_big_dca_straight.xcf | ||
| | dmu_big_straight.png | there is an xcf (gimp) file with elements in separate layers | |
| | dmu_bmu_mi_sigtobackground.png | ||
| | dmu_bmu_n_sigtobackground_2.png | This xcf file (Gimp native format) was used to make the png file of the same name. Typically the xcf file contains layers with separate info. In this case, there is the original plot containing just the dots, a separate layer for the lines connecting the dots, one layer for the legend. So if for example you want this plot without the lines, pick up this xcf file and use Gimp to turn off the layers you don't want. | |
| | dmu_bmu_n_sigtobackground_2.xcf | This xcf file (Gimp native format) was used to make the png file of the same name. Typically the xcf file contains layers with separate info. In this case, there is the original plot containing just the dots, a separate layer for the lines connecting the dots, one layer for the legend. So if for example you want this plot without the lines, pick up this xcf file and use Gimp to turn off the layers you don't want. | |
| | dmu_bmu_p_sigtobackground_2.png | ||
| | dmu_bmu_p_sigtobackground_2.xcf | ||
| | dmu_bmu_sigtobackground.png | ||
| | dr_lay1_sensor8x8_assy.gif | ||
| | dr_lay1_sensor8x_71.ps | ||
| | dr_lay2_sensor8x12_assy.gif | ||
| | dr_lay2_sensor8x_72.ps | ||
| | fifo_array.jpg | ||
| | fvtx_stations.png | ||
| | hirose_df30_series.pdf | ||
| | iFVTX_Assembly_3.jpg | ||
| | moss_bgd.gif | ||
| | neg_muon_sources.png | ||
| | neg_muon_sources.xcf | ||
| | phenix_big_sideview.png | ||
| | phenix_simple_sideview.jpg | ||
| | phenix_simplified_assy2.jpg | ||
| | pikdb_dcas.png | ||
| | pixel_block_diagram.jpg | ||
| | pulser.jpg | ||
| | raa_redbars.xcf | ||
| | raa_theory_MD_IVAN_both.xcf | ||
| | raa_theory_MD_IVAN_ldrd.png | ||
| | raa_theory_MD_IVAN_proposal.png | ||
| | sensor_wedge_B1_1-5-07.pdf | ||
| | sensor_wedge_B2_1-5-07.pdf | ||
| | si_endcap_rear_ckt_board_assy3.gif | ||
| | si_endcap_rear_ckt_board_assy3_dwg.gif | ||
| | si_tower_assy4a_3-7-06.gif | ||
| | signal_back.png | ||
| | sil_endcap_half_assy_3-06.gif | ||
| | sil_endcap_half_assy_detail_3-06.gif | ||
| | stat_sys_withfvtx.png | ||
| | svtx top assembly 2.jpg | ||
| | svtx top assembly2.jpg | ||
| | svtx top assembly2b.jpg | ||
| | svtx_FVTX_exploded.jpg | ||
| | svtx_Top_Assembly_with_iFVTX_1.jpg | Here are a couple of pictures that Roger Smith and I put together, for Sergey, to use in his IEEE presentation. These pictures show the four planes of the iFVTX detector located at the same Z locations as the planes for the FVTX array. Each of the three larger planes consists of two 8 X 11 FNAL sensor planes, mounted to a piece of TPG, set into a "window pane" board. The sensor arrays in each plane face each other with a 6. mm gap between the face of the backing boards. The first plane has a sensor array that is 8 X 4. One piece of information that would be very useful to understand the Z space required - would be the dimensional specifications for the connectors that will be mounted to the outside face of the backing or support boards, and how many will be needed. Cheers, Walt | |
| | svtx_assy_2-06c.gif | ||
| | svtx_assy_3-06.gif | ||
| | svtx_assy_section_noFVTX_isometric11-05.gif | ||
| | svtx_assy_section_no_FVTX_11-05.gif | ||
| | svtx_assy_spiro_layout_11-05.gif | ||
| | svtx_assy_vtx_cables_11-05.gif | ||
| | svtx_barrel_half_assy_5-11-07.jpg | ||
| | svtx_barrel_lay3_4_cable_terminator3.gif | ||
| | svtx_spiro_2nd_solution_array_drawing.gif | ||
| | svtx_top_assembly_2.jpg | ||
| | svtx_update_2-06.ppt | ||
| | thumbnail.py | ||
| | |||
| | obsolete: | ||
| | FVTXHalfAssy2.jpg | ||
| | FVTXHalfAssy2.pdf | ||
| | FVTXHalfAssy3.jpg | ||
| | FVTXHalfAssy5.jpg | ||
| | FVTXHalfAssy5.pdf | ||
| | FVTX_Disk_2_half_assy1.jpg | ||
| | FVTX_Half_Assy_4.jpg | ||
| | FVTX_Half_Assy_5.jpg | ||
| | FVTX_space11.png | Dear Dave and Melynda, Roger Smith has generated the attached drawing to show the space Between the VTX barrel layers and the FVTX cage and sensors. This picture incorporates the longer pixel ladder design as shown in Yasiyuki's first picture attached in his e-mail of this morning; namely the mounting block at layer 2 is outside the 20 degree acceptance line. This view also shows the previous design for the FVTX - nothing has been changed. Cheers, walt | |
| | FVTX_space_4-18-07.xcf | ||
| | PhenixCentralUpgradeAssy1.jpg | ||
| | PhenixCentralUpgradeAssy2.jpg | ||
| | PhenixCentralUpgradeAssy3.jpg | ||
| | obs | ||
| | FVTX_Disk_2_half_assy2.jpg | Roger and I have taken a first pass at trying to layout the HDI and wiring from the FVTX large disks in a way that provides reasonable clearances to mounting tabs and cooling tubes. The result is an HDI outline that features a narrow "tail" at the OD, with two of the 100-pin connectors for the extension cables. These tails would be bent at 90 degrees toward the magnet poles. The same exact HDI can be used on all wedges, but the tail is bent to one side or the other, depending on the side of the disk that particular wedge is mounted to (if the HDI are manufactured with a built-in bend, two different variants will be needed). Please refer to the attached drawing (pdf) for details. Also, look at the images below for a better idea of how this packages together. The HDI also feature two pin holes for alignment to the back-plane (and ultimately the Silicon detector), and three through holes for screws that would hold the wedges onto the support panels. Note that there is some flexibility in the position of the screw and pin holes. I would appreciate feedback about this configuration. Please note that we are using this configuration to define the locations of the mounting tabs in the support cage. This impacts the iFVTX group, as we are in the process of defining the envelope and mounting hole locations on their boards (i.e. please send me feedback sooner rather than later). Thanks! Eric HYTEC | |
| | FVTX_space_4-18-07.png | ||
|
Total today: 264 pictures Script last updated 21 June 2007 by Hubert van Hecke | |||