FVTX Design Revisions

ROC II Design Changes

3.3V_D_FO, which powers clock distribution, is not connected to a power pin. It should presumably be connected to the 3.3VD2 which is labeled for "FPGA C, D and BCO"
Capcacitors C1718, C2015 on the back-side of the board were shorted in both assembled boards because the ground pin solder pad of one and power pin solder pad of the other were placed quite close to each other. This layout should be changed to avoid bridges in production boards, if possible.
Signals TKLSB_SC, TKMSB_SC going to TLK2711 chip U501 are not properly connected to the Slow Control FPGA (U500). At the Slow Control FPGA, the signals are called SC_TKLSB and SC_TKMSB. There are also TWO of each of these signals at the SC FPGA, which are apparently connected to each other. Schematics should be fixed to have the same signals at U501 and U500, and the layout needs to be changed to connect them together, and remove one of the duplicate set of signals from U500.
Think we can live with this one :The SC_IN and SC_OUT signals going to/from the Hirose connectors, from/to the slow control FPGA are backwards. i.e SC_IN signals should be outputs from the FPGA to the FPHX chips and SC_OUT signals should be inputs to the FPGA from the FPHX chips. Primarily, this means terminations for all these signals need to be reversed either by rerouting the signals or by changing the termination locally, whichever makes more sense.
The outer pads for the hirose connectors on the board were supposed to have been made larger than the other pads, to allow a secure contact with the board, even through several connect/disconnects. This change to the pad structure does not appear to have been incorporated (layout from Dave Lauderdale). This must be incorporated into production board.
This requires no changes : Found that a number of data bits are swapped in layout compared to schematics for FPGA "B" and "D". The following pins are incorrect (but can just be fixed in schematics):
- DATA_OUT_B00(2) <--> DATA_OUT_B00(11)
- DATA_OUT_B00(6) <--> DATA_OUT_B00(15)
- DATA_OUT_B01(5) <--> DATA_OUT_B01(13)
- DATA_OUT_B01(7) <--> DATA_OUT_B01(15)
- DATA_OUT_B01(8) <--> SEND_DATA_0
This requires no changes Analog grounds to the wedges have grounds 0-3 going to Station 0, wedges 0-3. Analog grouds in the calibration system have grounds 0-3 going to wedge 0 for stations 0-3. Etc. So, analog grounds are mixed up with each other. Need to determine if there is a reasonable layout fix or if we end out tying analog grounds together. As it is, calibration system is quite noisy because of not having proper ground connections.
We would like to have in-line attenuators (10 dB, specified by Pat) added to the Cal_Inject lines at each hirose connector (32 in all).
We would like grounds of each calibration circuit tied together. Specification can be found here
Assembly Issues:
- Some capacitors on wedge digital power LDOs have been installed backwards, making the LDO inoperational. Dave Lauderdale says that it was not specified on assembly drawing (?).
- The BOM call out a right-angle connector for J4. We are unable to install a right-angle connector at J4; it interferes with U109 interferes. Please advise.
- J23 and U601 shield have no lead protrusion; their leads are too short to go all the way through the board thickness. We will do our best to solder these leads and holes.
- J3 tab hit the fuse (F1) and will not let it seat to the board. We can file the tabs down and make it fit; so let me know if you want us to do this.

Kapton HDI Design Changes

Change FPHX-->HDI bond pattern to match latest FPHX design bond pattern, and make associated schematics changes
Need bond pads for sensor bias ring.
ChipID should be numbered 1-13 on each side rather than 1-26 for module
Should revisit usage of vias in design, possibly other ways to improve manufacturability.
Any design changes to help heat dissipation?
Need screw hole at bottom of HDI
Should round edges around bottom tab

FPHX Design Changes

Invert bond pad pattern for FPHX-->sensor bond pads to match SiDet's request
Implement optimum W/L that Tom has chosen for input transistor
Try to improve threshold dispersion by optimizing the physical location of the shaper output and threshold comparator
Enable R/O on either serial output line, serialout1 or serialout2 or both
Add 7th time stamp bit (drop last word bit - we don't use it)
Fix the logic bug that Jim found that results in a mis-id of time-stamped events under certain timing conditions

Assembly Fixture Design Changes

Fix chip spacing on chip placement fixture to match chip spacing on HDI. - Updated Drawing now available, in Fixtures directory
Fabrication: Chip alignment out of spec, chip placement has slight interference, chip placement has extra ledge
Sensor placement jig developed crack: Suggestion to make out of Al instead of acrylic. Could be a problem for chip placement
Chip placement needs stops, Bert glued wire down, Dave Lee has suggested plan for machined stops (Bert approves)
Fixtures have chip-to-chip spacing of 9.46 mm (Matches PCB HDI design, does not match Kapton HDI design (9.6 mm spacing))

ROC-2 Schematic Comments

Remaining comments on July 19, 2010 Version: This should be a comprehensive list of remaining issue as of 19-July-10.

CHECK Make sure receptacles for 12-fiber fiber optics are specified correctly on BOM. Were not specified correctly for prototype.
NEW 1-Oct-10 pg. 19, 26, 33 and 40: one half of HFBR DIN connections (DIN0 through DIN3) have wrong polarity connection to TLKs. e.g. (DIN0+)-->TXN and (DIN0-)-->TXP.
STILL PRESENT 28-Sep-10: pg 42 - U501 (TLK2711) is missing connection of LOOPEN, PRBSEN, TESTEN to ground
NEW 24-Sep-10: pg. 39 - 2.5V is being connected through capacitors to ground but on other FPGA power pages it is 1.5V.
NEW 16-Sep-10: pg 26: U201, 202, 203+204 show +1.5V going to enable pin rather than +2.5V
NEW 16-Sep-10: pg. 42: U601 has pin 13 (RD+)-->10k resistor but I think the 10k resistor is instead supposed to connect to pin 2 (TxFAULT)
NEW 16-Sep-10: pg. 42: LOS signal connection out is different from what it was on prototype, and in datasheet suggested schematics. Not sure if it is actually wrong or not, but should be looked at
NEW 16-Sep-10: pg. 63, 64, 65, 66, 67 have 1/2 of the pins connected to +2.5 V (correct) and 1/2 (pins 9+16) still connected to +3.3V
NEW: pg 63 - U735 (MAX9174) is missing 100 ohm termination resistor on input lines.
NEW: Need the slow control TLK enable (SC_ENABLE) to go to the JTAG FPGA.
Need to put fusing back in on the power because there will not be distributions boards with fusing for the ROC.
MAX9317AECJ parts need to be provided with 2.5V power instead of 3.3V. 100 Ohm termination resistor on clock lines should also be removed. (pgs. 63, 64, 65, 66, 67)
Terminations on pulser channel address and enable lines should be changed from 1K to 5K (R1349, 1350, 1351, 1363, 1352, 1353, 1354, 1364, 1355, 1356, 1357, 1365, 1358, 1359, 1360 and 1366)
150 pF pulse shaping capacitor is missing between the pulse output amplifier stages and analog ground. Specifically: add a 150 pF ceramic capacitor in parallel with each of R458, R457, R319 and R459 (pgs. 57-60).
FPGA Reset signal was changed from R4 to T26, but should have been left on R4.

Remaining comments on June 14, 2010 Version: This should be a comprehensive list of remaining issue as of 15-July-10.

Need to put fusing back in on the power because there will not be distributions boards with fusing for the ROC.
U62 part number HFBR-5720 should be updated to the new replacement part AFBR-57M5APZ.
One reset is going from SC FPGA to all data FPGAs, but had at one point requested 4 individual resets. Decided one reset is o.k.
p.55 U629 should have DGND_14 -> DGND_15
On all main FPGAs: VCCPLX and VCOMPL inputs are connected together but not to 1.5 V for FPGAs B, C, D. 0.01 uF is not added to them also.
JTAG FPGA should have TX data bits [14:15], and RX bits [9:15]. SC FPGA should have TX bits [0:13] and RX bits [0:8] to match the FEM FO output nomenclature. These fixes are not critical (we will program accordingly if not fixed) but: ***Would like all 16 RX bits to go to SC FPGA rather than subset to make for better syncing of TLKs***
All clocks should be 100 Ohm terminated explicitly close to the FPGA. - think this is done -
MAX9317AECJ parts need to be provided with 2.5V power instead of 3.3V. 100 Ohm termination resistor on clock lines should also be removed. (pgs. 63, 64, 65, 66, 67)
MAX 9153 clock distribution chips have VCC incorrectly shorted to ground - pg. 68
Terminations on pulser channel address and enable lines should be changed from 1K to 5K (R1349, 1350, 1351, 1363, 1352, 1353, 1354, 1364, 1355, 1356, 1357, 1365, 1358, 1359, 1360 and 1366)
150 pF pulse shaping capacitor is missing between the pulse output amplifier stages and analog ground. Specifically: add a 150 pF ceramic capacitor in parallel with each of R458, R457, R319 and R459 (pgs. 57-60).
The LCKREFN on the slow control TLK2711 is tied low and it should be tied high. (pg. 42)
LAYOUT: Request to keep sides of Hirose connectors clear of components to allow for easier detachment of connectors.

Comments on November 23, 2009 Version:

Need to put fusing back in on the power because there will not be distributions boards with fusing for the ROC.
NOTE from ROC-1: LV schematics power distribution and layout does not match. Is this corrected on ROC-v2?
U62 part number HFBR-5720 should be updated to the new replacement part AFBR-57M5APZ.
U62 is missing RxLOS connection through 10kohm resistor to V_CC,R
Data lines on TLK2771 chips should have ~100 nF coupling capacitors between TLK2771 and HFBR parts.
RESET on the main FPGA should arrive from the Slow Control FPGA. It does not look like this from the schematics. Slow Control FPGA is not being reseted through a pin but either by the SC data.
CLK_FPGA_A(..) is not defined. This is probably OUT_CLK_A(...)
TKMSB_Axxx, TKLSB_Axxx (e.t.c are not connected). Put them to the left part of the main FPGA bank that has SC_IN_A and so on signals.
On the FO page for FPGA C and D. A should be changed to C or D.
p.55 U629 should have DGND_14 -> DGND_15
p.64-67 should be referring to CLK_Out_Wedgexx instead of CLK_BCO_Wedgexx
p.68 I do not see distribution of this clock to FPGAs (OUT_CLK_A(...) or CLK_FPGA_A(..) up to you).
On all main FPGAs: VCCPLX inputs connected together but not to 1.5 V. 0.01 uF is not added to them also.
VCCPLs and VCOMPLs still need to be connected on FPGAs B,C,D. FPGA appears to be correct.
JTAG FPGA does not need LEDs and testpoints
JTAG FPGA should have TX data bits [14:15], and RX bits [9:15]. SC FPGA should have TX bits [0:13] and RX bits [0:8] to match the FEM FO output nomenclature.

Comments on October 5, 2009 Version:

Station 0 chips should be numbered 1-5 on each side rather than 1-10 (P100, ...). - fixed
Station 0 SC_in and OUT_CLK signals seem to be swapped from what they should be on the data connectors. Decided this was o.k., even though different from Stations 2-4. HDIs, Interconnects are consistent with this order
FPGA-A and B both seemd to connect to "Wedge 0" rather than "Wedge 0" and "Wedge 1". - fixed
Slow controls signals SC_IN, SC_EN and SC_OUT seem to be missing (should go between Slow Controls FPGA and Main FPGAs). - fixed
Add SC_IN_A(B,C,D),SC_EN_A and SC_OUT_A between SC and each of the main FPGAs. - fixed
Do not see OUT_CLK (125 MHz) on main FPGAs
All clocks should be 100 Ohm terminated explicitly close to the FPGA.
p.9 and so on. All TLKs keep two 0 ohm resistors. One need to be removed or changed in value. p.34 has it correctly. - fixed
SC and JTAG FPGAs should share the FO I/O data same way as for iFVTX ROC
Remove Test Points and LEDs on JTAG FPGA - fixed
p.33 remove TPs other then TP25 and TP27 - fixed
p 33 and below. Check that line is connected to CLKA_b pin of MAX 2-to-10 distribution chip. I see a lot of missing lines. - fixed
Make sure that we use internal terminated version of this chip. Othervise 100 ohm termination should be added to both CLKA and CLKB lines. (Not sure why we even need it in a current design, but it seem to work for iFVTX ROC and resistor can easily be removed if not needed)
p.32 and below No TPs needed but the one on the output of the oscillator. They take up space and if the chip's package is not BGA, I would just test signals on the pins of the chip and save space. - fixed
Add termination resistors to all inputs and term arrays to all the outputs
For both FPGAs: BCO_CLK_IN_p should connect to T28, BCO_CLK_IN_N to R30.
For both FPGAs: OUT_CLK_p connect to R2, OUT_CLK_n to R5.
For SC FPGA, RX_CLK_p connect to T3, RX_CLK_n to T5.
Clock distribution chips (MAX 9153) have VCC incorrectly shorted to ground.
Station 0 connectors should go back to old version to match HDIs as laid out
JTAG FPGA has the power incorrect (report from Sergey, needs to look up details) - fixed
Calib needs some filter capacitors added (to help remove pickup that was found on ROC-1 calibration signals)
The calibration circuit currently ties all analog grounds of 16 wedges together. Pat is working to determine a way to fix this.
The Slow Control fiber optic is wired up in loop-back mode and needs to be fixed. Other fiber optic is wired correctly. - fixed
The LCKREFN on the slow control TLK2711 is tied low and it should be tied high.

FEM Interface Comments

Pull-up ressitor R26(27) on ISL3295 should be changed from 10k to 1-3k (according to data sheet).
JTAG connector needs connection to 2.5 Volt power.
USB connector should be rotated 180 degrees.
Extra ethernet debugging connections requested, specified by Pat.
BCO_CLK, SCK (other?) differential pairs (VBG0) that are being sent to the backplane are being sent on inappropriate pins. Select appropriate pins for propagation of clocks.

FEM Prototype Comments

Front panel needs to have SC and Main FPGA LED labels swapped.
Power on U28, U26 (2.5V and 3.3V) is backwards. Our fix was to swap the FB resistors on the two voltage regulators. Some redundant resistors were also removed (need to check board).
Need coupling capacitors between HFBR782 data lines and TLK2711s
Need to provide TX_CLK to all TLK2711s (missing from all receivers that connect to U15 and U41)
Above means that a 125 MHz oscillator must be added to board. Must have same specifications as oscillator on ROC board.
NI connector (J1) has incorrect pinout for NI-6534 module. Please see NI 6534 data sheet , Page 2, for correct pinout.
TLK2711 won't work for communication with DCM's TLK2501. Need to replace TLK2711's with TLK2501's.
JTAG connector needs connection to 2.5 Volt power.
Terminate all unused LVDS outputs from the FO receiver with 100 ohm terminations.
LED power and grounds are hooked up backwards.
FEM address currently setable with front-panel dial-in number (which doesn't fit on front panel) should be replaced with dip switches.

Last update by Melynda Brooks