Various FPGA codes can be found posted on the FVTX web page--> DAQ -->
FPGA Code . A summary of the packages is given here:
- ROC_slow_control_HDI_Module - slow control code for the ROC
slow control FPGA. This module controls the slow control information
that goes to the wedges and the data FPGAs.
- ROC_slow_control_HDI_Module_large_wedge - slow control
code specifically for reading out
large wedges without an extension cable. This allows appropriate
delivery of BCO and RESET signals
to the wedges when they are plugged into the "B" or "D" locations
and also sends the BCO clock
to the data FPGA. Other than that, the code should be identical
to ROC_slow_control_HDI_Module.
- ROC_FVTX - ROC data FPGA code for locations "A" or "C".
Note that A and C locations have
different FPGA pinouts than "B" and "D" locations, so two different
code versions are needed.
- ROC_FVTX_B_D - ROC data FPGA code for locations "B" or "D".
- ROC_FVTX_B_D_large_wedge - ROC data FPGA code to be
used only for "B" or "D" locations, and
readout of a large wedge with no extension cable. The only difference
between this code and ROC_FVTX_B_D is that the BCO_CLK is extracted from
a line coming from the slow control FPGA rather
than from the clock distribution circuitry (which in this case is being
used for RESET signals).
- FEM_FVTX - FEM FPGA code for the handling of data in
the FEM. This gets downloaded into the
Virtex 4 FPGA.
- SlowControl_FEM - FEM FPGA code for the handling of
slow control communication in the FEM. This
gets downloaded into the Spartan-3 chip on the FEM board.
- FEM_IB - FEM Interface Board code. This code handles
distribution of the slow control
data coming in on USB or ethernet, distribution of the BCO_CLK and
START signals to the clock
distribution boards, distribution of the LVL1-trigger to the FEM
boards. It is also used to
remotely program the FPGAs on the ROC if that is called for.
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