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FVTX ROC Card
ROC V2 Design:
- ROC Production Design Package
- ROC II design revisions can be found here
- ROC Data FPGA Code Flow Diagram (.docx)
- ROC Data Fiber Mapping Info (.xlsx)
- ROC-V2 Schematics, FINAL , FINAL - SEARCHABLE PDF
- ROC-V2 Schematics , April 15, 2011 - SEARCHABLE PDF (first two prototype boards)
- ROC Primary Side (pdf), ROC Secondary Side (pdf), DXF , and Dimensioned Layout(jpg) February 16, 2011
- ROC-V2 Bill of Materials (excel) July 19, 2011
- ROC-V2 layout design package January 21, 2011
- Blue Wire Patch for SC LSB signal
- TLK2711 "Minimal Protocol" Paper (for synchronization)
- Pin 1 Signal Tracing from HDI to ROC , (ppt) and pdf Updated July 7, 2010
- ROC-V2 Outline from HYTEC (pdf) , and dxf Updated to add 2" to outer radius, April 12, 2010
- ROC-V2 Main FPGA, Slow Control FPGA, and JTAG FPGA Pinout Specification March 22, 2011
- ROC Power, Heat Load Sources (pdf)
- Running tally of suggested ROC-V2 Revisions can be found here
- ROC_V1 fixes needed to make FO Communication Work
- ROC-V1 Schematics , and Bottom Layout , and Top Layout .
- Full set of ROC Design Files (directory)
- ROC-V2 Bare Board Photos, March 22, 2011
- Photos of ROC-V1 Test Stand , and more photos, in FEM test stand
- ROC-II, no components
- ROC-II, with components
- ROC-II, annotated
- ROCs assembled onto cooling plate, mounted on the cage, then cabled up
Last update Wednesday, 02-Oct-2013 12:58:18 MDT by Matt Durham (durham@lanl.gov)