======================================================================= Expedition PCB - Pinnacle - Version PCB2004_040223.1326 2004 ======================================================================= Job Directory: C:\07_JOBPHIL\CERN_PROTOTYPE_20_lyrs\PCB\ Design Status Report: C:\07_JOBPHIL\CERN_PROTOTYPE_20_lyrs\PCB\LogFiles\DesignStatus_73.txt Tue Mar 20 18:07:38 2007 ======================================================================= DESIGN STATUS ======================================================================= Board Size Extents ............ 13.35 X 7.69 (in) Route Border Extents .......... 6.25 X 7.64 (in) Actual Board Area ............. 102.64 (in) Actual Route Area ............. 47.72 (in) Placement Areas: Name Available Required Required/Available Entire Board 205.28 Sq. (in) 40.08 Sq. (in) 19.53 % Room: 57.35 Sq. (in) 0 Sq. (in) 0.00 % Pins .......................... 9162 Pins per Route Area ........... 191.99 Pins/Sq. (in) Layers ........................ 20 Layer 1 is a signal layer Trace Widths .......... 5, 6, 7.87, 8, 10, 20, 25 Layer 2 is a Positive Plane Layer with nets DGND Trace Widths .......... None. Layer 3 is a signal layer Trace Widths .......... 4, 5, 10 Layer 4 is a Positive Plane Layer with nets DGND Trace Widths .......... None. Layer 5 is a signal layer Trace Widths .......... 4, 5 Layer 6 is a signal layer Trace Widths .......... None. Layer 7 is a signal layer Trace Widths .......... 4 Layer 8 is a signal layer Trace Widths .......... 4, 5 Layer 9 is a Positive Plane Layer with nets DGND Trace Widths .......... None. Layer 10 is a signal layer Trace Widths .......... 6 Layer 11 is a signal layer Trace Widths .......... 6 Layer 12 is a Positive Plane Layer with nets DGND Trace Widths .......... None. Layer 13 is a signal layer Trace Widths .......... 4, 5 Layer 14 is a signal layer Trace Widths .......... 4 Layer 15 is a signal layer Trace Widths .......... None. Layer 16 is a signal layer Trace Widths .......... 4, 25 Layer 17 is a Positive Plane Layer with nets DGND Trace Widths .......... None. Layer 18 is a signal layer Trace Widths .......... 4, 5 Layer 19 is a Positive Plane Layer with nets DGND Trace Widths .......... None. Layer 20 is a signal layer Trace Widths .......... 5, 6, 10, 20, 25, 30, 50 Nets .......................... 1816 Connections ................... 6794 Open Connections .............. 1488 Differential Pairs ............ 25 Differential Pair Names: ADC_DATA(0)+ ADC_DATA(0)- ADC_DATA(1)+ ADC_DATA(1)- ADC_DATA(2)+ ADC_DATA(2)- ADC_DATA(3)+ ADC_DATA(3)- ADC_DATA(4)+ ADC_DATA(4)- ADC_DATA(5)+ ADC_DATA(5)- ADC_DATA(6)+ ADC_DATA(6)- ADC_DATA(7)+ ADC_DATA(7)- ADC_DATA(8)+ ADC_DATA(8)- ADC_DATA(9)+ ADC_DATA(9)- ADC_DATA(10)+ ADC_DATA(10)- ADC_DATA(11)+ ADC_DATA(11)- ADC_DATA(12)+ ADC_DATA(12)- ADC_DATA(13)+ ADC_DATA(13)- ADC_DATA(14)+ ADC_DATA(14)- ADC_DATA(15)+ ADC_DATA(15)- ADC_120MHz+ ADC_120MHz- CLKA_N CLKA_P CLKB_N CLKB_P CLKC_N CLKC_P CLKD_N CLKD_P CLKE_N CLKE_P CLKF_N CLKF_P CLKG_N CLKG_P CLKH_N CLKH_P Percent Routed ................ 78.14 % Netline Length ................ 1,413.01 (in) Netline Manhattan Length ...... 1,724.61 (in) Total Trace Length ............ 2,917.95 (in) Trace Widths Used (th) ........ 4, 5, 6, 7.87, 8, 10, 20, 25, 30, 50 Vias .......................... 6258 Via Span Name Quantity 1-20 050VIA 32 018VIA_8 1134 025VIA_10 1143 035VIA 394 018VIA_8_14mask-bga 2339 1-10 VIA020_010 1 025VIA_10 545 035VIA 90 11-20 025VIA 2 025VIA_10 521 035VIA 57 Teardrops....................... 0 Breakouts....................... 0 Virtual Pins.................... 0 Guide Pins ..................... 0 Parts Placed .................. 1852 Parts Mounted on Top ...... 363 SMD ................... 325 Through ............... 38 Test Points ........... 0 Mechanical ............ 0 Parts Mounted on Bottom ... 1489 SMD ................... 1488 Through ............... 1 Test Points ........... 0 Mechanical ............ 0 Edge Connector Parts ...... 0 Parts not Placed .............. 1 Nested Cells .................. 0 Jumpers ....................... 0 Through Holes ................. 5409 Holes per Board Area ...... 52.7 Holes/Sq. (in)