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Expedition PCB - Pinnacle - Version PCB2004_040223.1326 2004
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Job Directory:        C:\07_JOBPHIL\CERN_PROTOTYPE_20_lyrs\PCB\

Design Status Report: C:\07_JOBPHIL\CERN_PROTOTYPE_20_lyrs\PCB\LogFiles\DesignStatus_72.txt

Tue Mar 20 15:54:25 2007

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DESIGN STATUS
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Board Size Extents  ............ 13.35 X 7.69 (in)
Route Border Extents  .......... 6.25 X 7.64 (in)
Actual Board Area  ............. 102.64 (in)
Actual Route Area  ............. 47.72 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    205.28 Sq. (in)   40.08 Sq. (in)    19.53 %
           Room:                 57.35 Sq. (in)    0 Sq. (in)        0.00 %

Pins  .......................... 9162
Pins per Route Area  ........... 191.99 Pins/Sq. (in)

Layers  ........................ 20
    Layer 1 is a signal layer
        Trace Widths  .......... 5, 6, 7.87, 8, 10, 20, 25
    Layer 2 is a Positive Plane Layer with nets
        DGND
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... 4, 5, 10
    Layer 4 is a Positive Plane Layer with nets
        +1.5V
        +1.2V-D1
        +1.2V-D2
        +1.8V
        +1.8V_QDRA
        +1.8V_QDRA55
        +1.8V_QDRB
        +1.8V_QDRB55
        +2.5V
        +2.5V-D
        +3.3V
        +3.3V-D
        +3.3V_B
        +5V
        +5V_B
        +12V
        +12V_B
        -5V
        -12V
        -12V_B
        Trace Widths  .......... None.
    Layer 5 is a signal layer
        Trace Widths  .......... 4, 5
    Layer 6 is a signal layer
        Trace Widths  .......... None.
    Layer 7 is a signal layer
        Trace Widths  .......... 4
    Layer 8 is a signal layer
        Trace Widths  .......... 4, 5
    Layer 9 is a Positive Plane Layer with nets
        DGND
        Trace Widths  .......... None.
    Layer 10 is a signal layer
        Trace Widths  .......... 6
    Layer 11 is a signal layer
        Trace Widths  .......... 6
    Layer 12 is a Positive Plane Layer with nets
        DGND
        Trace Widths  .......... None.
    Layer 13 is a signal layer
        Trace Widths  .......... 4, 5
    Layer 14 is a signal layer
        Trace Widths  .......... 4
    Layer 15 is a signal layer
        Trace Widths  .......... None.
    Layer 16 is a signal layer
        Trace Widths  .......... 4, 25
    Layer 17 is a Positive Plane Layer with nets
        +2.5V
        +5V
        Trace Widths  .......... None.
    Layer 18 is a signal layer
        Trace Widths  .......... 4, 5
    Layer 19 is a Positive Plane Layer with nets
        DGND
        Trace Widths  .......... None.
    Layer 20 is a signal layer
        Trace Widths  .......... 5, 6, 10, 20, 25, 30, 40, 50

Nets  .......................... 1816
Connections  ................... 6807
Open Connections  .............. 1093
Differential Pairs  ............ 25
Differential Pair Names:   ADC_DATA(0)+   ADC_DATA(0)-
                           ADC_DATA(1)+   ADC_DATA(1)-
                           ADC_DATA(2)+   ADC_DATA(2)-
                           ADC_DATA(3)+   ADC_DATA(3)-
                           ADC_DATA(4)+   ADC_DATA(4)-
                           ADC_DATA(5)+   ADC_DATA(5)-
                           ADC_DATA(6)+   ADC_DATA(6)-
                           ADC_DATA(7)+   ADC_DATA(7)-
                           ADC_DATA(8)+   ADC_DATA(8)-
                           ADC_DATA(9)+   ADC_DATA(9)-
                           ADC_DATA(10)+   ADC_DATA(10)-
                           ADC_DATA(11)+   ADC_DATA(11)-
                           ADC_DATA(12)+   ADC_DATA(12)-
                           ADC_DATA(13)+   ADC_DATA(13)-
                           ADC_DATA(14)+   ADC_DATA(14)-
                           ADC_DATA(15)+   ADC_DATA(15)-
                           ADC_120MHz+   ADC_120MHz-
                           CLKA_N   CLKA_P
                           CLKB_N   CLKB_P
                           CLKC_N   CLKC_P
                           CLKD_N   CLKD_P
                           CLKE_N   CLKE_P
                           CLKF_N   CLKF_P
                           CLKG_N   CLKG_P
                           CLKH_N   CLKH_P
                           
Percent Routed  ................ 83.99 %

Netline Length  ................ 1,275.48 (in)
Netline Manhattan Length  ...... 1,562.3 (in)
Total Trace Length  ............ 2,911.05 (in)

Trace Widths Used (th)  ........ 4, 5, 6, 7.87, 8, 10, 20, 25, 30, 40, 50
Vias  .......................... 6229
Via Span  Name                   Quantity
   1-20   050VIA                 4
          018VIA_8               1134
          025VIA_10              1143
          035VIA                 393
          018VIA_8_14mask-bga    2339
   1-10   VIA020_010             1
          025VIA_10              545
          035VIA                 90
  11-20   025VIA                 2
          025VIA_10              521
          035VIA                 57

Teardrops....................... 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 1852
    Parts Mounted on Top  ...... 364
        SMD  ................... 326
        Through  ............... 38
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 1488
        SMD  ................... 1487
        Through  ............... 1
        Test Points  ........... 0
        Mechanical  ............ 0
    Edge Connector Parts  ...... 0

Parts not Placed  .............. 1

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 5380
    Holes per Board Area  ...... 52.42 Holes/Sq. (in)