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Expedition PCB - Pinnacle - Version PCB2004_040223.1326 2004
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Job Directory:        C:\06_JOB_ISR4\CERN_PROTOTYPE\PCB\

Design Status Report: C:\06_JOB_ISR4\CERN_PROTOTYPE\PCB\LogFiles\DesignStatus_55.txt

Wed Feb 14 11:38:01 2007

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DESIGN STATUS
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Board Size Extents  ............ 6.3 X 7.69 (in)
Route Border Extents  .......... 6.25 X 7.64 (in)
Actual Board Area  ............. 48.42 (in)
Actual Route Area  ............. 47.72 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    96.83 Sq. (in)    39.37 Sq. (in)    40.66 %
           Room:                 57.35 Sq. (in)    0 Sq. (in)        0.00 %

Pins  .......................... 9030
Pins per Route Area  ........... 189.23 Pins/Sq. (in)

Layers  ........................ 16
    Layer 1 is a signal layer
        Trace Widths  .......... 5, 6, 7.87, 8, 10, 20
    Layer 2 is a Positive Plane Layer with nets
        DGND
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... 4, 5
    Layer 4 is a Positive Plane Layer with nets
        +1.5V
        Trace Widths  .......... None.
    Layer 5 is a signal layer
        Trace Widths  .......... None.
    Layer 6 is a signal layer
        Trace Widths  .......... 4, 5
    Layer 7 is a Positive Plane Layer with nets
        DGND
        Trace Widths  .......... None.
    Layer 8 is a signal layer
        Trace Widths  .......... None.
    Layer 9 is a signal layer
        Trace Widths  .......... 6
    Layer 10 is a Positive Plane Layer with nets
        DGND
        Trace Widths  .......... None.
    Layer 11 is a signal layer
        Trace Widths  .......... 4, 5
    Layer 12 is a signal layer
        Trace Widths  .......... 4
    Layer 13 is a Positive Plane Layer with nets
        +2.5V
        Trace Widths  .......... None.
    Layer 14 is a signal layer
        Trace Widths  .......... 4, 5
    Layer 15 is a Positive Plane Layer with nets
        DGND
        Trace Widths  .......... None.
    Layer 16 is a signal layer
        Trace Widths  .......... 5, 6, 10, 20

Nets  .......................... 1786
Connections  ................... 6652
Open Connections  .............. 3435
Differential Pairs  ............ 25
Differential Pair Names:   ADC_DATA(0)+   ADC_DATA(0)-
                           ADC_DATA(1)+   ADC_DATA(1)-
                           ADC_DATA(2)+   ADC_DATA(2)-
                           ADC_DATA(3)+   ADC_DATA(3)-
                           ADC_DATA(4)+   ADC_DATA(4)-
                           ADC_DATA(5)+   ADC_DATA(5)-
                           ADC_DATA(6)+   ADC_DATA(6)-
                           ADC_DATA(7)+   ADC_DATA(7)-
                           ADC_DATA(8)+   ADC_DATA(8)-
                           ADC_DATA(9)+   ADC_DATA(9)-
                           ADC_DATA(10)+   ADC_DATA(10)-
                           ADC_DATA(11)+   ADC_DATA(11)-
                           ADC_DATA(12)+   ADC_DATA(12)-
                           ADC_DATA(13)+   ADC_DATA(13)-
                           ADC_DATA(14)+   ADC_DATA(14)-
                           ADC_DATA(15)+   ADC_DATA(15)-
                           ADC_120MHz+   ADC_120MHz-
                           CLKA_N   CLKA_P
                           CLKB_N   CLKB_P
                           CLKC_N   CLKC_P
                           CLKD_N   CLKD_P
                           CLKE_N   CLKE_P
                           CLKF_N   CLKF_P
                           CLKG_N   CLKG_P
                           CLKH_N   CLKH_P
                           
Percent Routed  ................ 48.38 %

Netline Length  ................ 2,901.83 (in)
Netline Manhattan Length  ...... 3,606.23 (in)
Total Trace Length  ............ 348.75 (in)

Trace Widths Used (th)  ........ 4, 5, 6, 7.87, 8, 10, 20
Vias  .......................... 4646
Via Span  Name                   Quantity
   1-16   025VIA                 6
          018VIA_8               1134
          035VIA                 229
          025VIA_10              717
          018VIA_8_14mask-bga    2318
   1-8    025VIA                 3
          VIA020_010             1
          025VIA_10              149
   9-16   025VIA                 3
          025VIA_10              86

Teardrops....................... 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 1778
    Parts Mounted on Top  ...... 396
        SMD  ................... 377
        Through  ............... 19
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 1382
        SMD  ................... 1378
        Through  ............... 4
        Test Points  ........... 0
        Mechanical  ............ 0
    Edge Connector Parts  ...... 0

Parts not Placed  .............. 5

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 4758
    Holes per Board Area  ...... 98.27 Holes/Sq. (in)