======================================================================= Expedition PCB - Pinnacle - Version PCB2004_040223.1326 2004 ======================================================================= Job Directory: C:\06_JOB_ISR4\CERN_PROTOTYPE\PCB\ Design Status Report: C:\06_JOB_ISR4\CERN_PROTOTYPE\PCB\LogFiles\DesignStatus_50.txt Wed Jan 31 15:33:05 2007 ======================================================================= DESIGN STATUS ======================================================================= Board Size Extents ............ 16.63 X 11.93 (in) Route Border Extents .......... 6.25 X 7.64 (in) Actual Board Area ............. 198.32 (in) Actual Route Area ............. 47.72 (in) Placement Areas: Name Available Required Required/Available Entire Board 396.65 Sq. (in) 38.9 Sq. (in) 9.81 % Room: 57.35 Sq. (in) 0 Sq. (in) 0.00 % Pins .......................... 8614 Pins per Route Area ........... 180.51 Pins/Sq. (in) Layers ........................ 16 Layer 1 is a signal layer Trace Widths .......... 5, 6, 7.87, 8, 10, 20 Layer 2 is a Positive Plane Layer with nets DGND Trace Widths .......... None. Layer 3 is a signal layer Trace Widths .......... 4, 5 Layer 4 is a Positive Plane Layer with nets +1.5V Trace Widths .......... None. Layer 5 is a signal layer Trace Widths .......... None. Layer 6 is a signal layer Trace Widths .......... 4, 5 Layer 7 is a Positive Plane Layer with nets DGND Trace Widths .......... None. Layer 8 is a signal layer Trace Widths .......... None. Layer 9 is a signal layer Trace Widths .......... 6 Layer 10 is a Positive Plane Layer with nets DGND Trace Widths .......... None. Layer 11 is a signal layer Trace Widths .......... 4, 5 Layer 12 is a signal layer Trace Widths .......... None. Layer 13 is a Positive Plane Layer with nets +2.5V Trace Widths .......... None. Layer 14 is a signal layer Trace Widths .......... 4, 5 Layer 15 is a Positive Plane Layer with nets DGND Trace Widths .......... None. Layer 16 is a signal layer Trace Widths .......... 5, 6, 10, 20 Nets .......................... 1782 Connections ................... 6123 Open Connections .............. 4086 Differential Pairs ............ 25 Differential Pair Names: ADC_DATA(0)+ ADC_DATA(0)- ADC_DATA(1)+ ADC_DATA(1)- ADC_DATA(2)+ ADC_DATA(2)- ADC_DATA(3)+ ADC_DATA(3)- ADC_DATA(4)+ ADC_DATA(4)- ADC_DATA(5)+ ADC_DATA(5)- ADC_DATA(6)+ ADC_DATA(6)- ADC_DATA(7)+ ADC_DATA(7)- ADC_DATA(8)+ ADC_DATA(8)- ADC_DATA(9)+ ADC_DATA(9)- ADC_DATA(10)+ ADC_DATA(10)- ADC_DATA(11)+ ADC_DATA(11)- ADC_DATA(12)+ ADC_DATA(12)- ADC_DATA(13)+ ADC_DATA(13)- ADC_DATA(14)+ ADC_DATA(14)- ADC_DATA(15)+ ADC_DATA(15)- ADC_120MHz+ ADC_120MHz- CLKA_N CLKA_P CLKB_N CLKB_P CLKC_N CLKC_P CLKD_N CLKD_P CLKE_N CLKE_P CLKF_N CLKF_P CLKG_N CLKG_P CLKH_N CLKH_P Percent Routed ................ 33.27 % Netline Length ................ 2,908.88 (in) Netline Manhattan Length ...... 3,592.19 (in) Total Trace Length ............ 317.63 (in) Trace Widths Used (th) ........ 4, 5, 6, 7.87, 8, 10, 20 Vias .......................... 4408 Via Span Name Quantity 1-16 025VIA 7 018VIA_8_14mask-bga 2318 025VIA_10 600 035VIA 229 018VIA_8 1155 1-8 VIA020_010 1 025VIA 33 020VIA_10 1 025VIA_10 33 9-16 025VIA 3 025VIA_10 28 Teardrops....................... 0 Breakouts....................... 0 Virtual Pins.................... 0 Guide Pins ..................... 0 Parts Placed .................. 1539 Parts Mounted on Top ...... 400 SMD ................... 382 Through ............... 18 Test Points ........... 0 Mechanical ............ 0 Parts Mounted on Bottom ... 1139 SMD ................... 1135 Through ............... 4 Test Points ........... 0 Mechanical ............ 0 Edge Connector Parts ...... 0 Parts not Placed .............. 36 Nested Cells .................. 0 Jumpers ....................... 0 Through Holes ................. 4663 Holes per Board Area ...... 23.51 Holes/Sq. (in)