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Expedition PCB - Pinnacle - Version PCB2004_040223.1326 2004
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Job Directory:        C:\06_JOB_ISR4\CERN_PROTOTYPE\PCB\

Design Status Report: C:\06_JOB_ISR4\CERN_PROTOTYPE\PCB\LogFiles\DesignStatus_42.txt

Mon Jan 22 11:13:25 2007

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DESIGN STATUS
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Board Size Extents  ............ 16.63 X 11.93 (in)
Route Border Extents  .......... 6.25 X 7.64 (in)
Actual Board Area  ............. 198.32 (in)
Actual Route Area  ............. 47.72 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    396.65 Sq. (in)   38.45 Sq. (in)    9.69 %
           Room:                 57.35 Sq. (in)    0 Sq. (in)        0.00 %

Pins  .......................... 8304
Pins per Route Area  ........... 174.01 Pins/Sq. (in)

Layers  ........................ 16
    Layer 1 is a signal layer
        Trace Widths  .......... 5, 6, 7.87, 8, 10
    Layer 2 is a signal layer
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... 5
    Layer 4 is a Positive Plane Layer with nets
        +1.5V
        Trace Widths  .......... None.
    Layer 5 is a signal layer
        Trace Widths  .......... None.
    Layer 6 is a signal layer
        Trace Widths  .......... None.
    Layer 7 is a signal layer
        Trace Widths  .......... None.
    Layer 8 is a signal layer
        Trace Widths  .......... None.
    Layer 9 is a signal layer
        Trace Widths  .......... None.
    Layer 10 is a signal layer
        Trace Widths  .......... None.
    Layer 11 is a signal layer
        Trace Widths  .......... None.
    Layer 12 is a signal layer
        Trace Widths  .......... None.
    Layer 13 is a Positive Plane Layer with nets
        +2.5V
        Trace Widths  .......... None.
    Layer 14 is a signal layer
        Trace Widths  .......... 5
    Layer 15 is a signal layer
        Trace Widths  .......... None.
    Layer 16 is a signal layer
        Trace Widths  .......... 5, 6, 10

Nets  .......................... 1790
Connections  ................... 5517
Open Connections  .............. 4340
Differential Pairs  ............ 25
Differential Pair Names:   ADC_DATA(0)+   ADC_DATA(0)-
                           ADC_DATA(1)+   ADC_DATA(1)-
                           ADC_DATA(2)+   ADC_DATA(2)-
                           ADC_DATA(3)+   ADC_DATA(3)-
                           ADC_DATA(4)+   ADC_DATA(4)-
                           ADC_DATA(5)+   ADC_DATA(5)-
                           ADC_DATA(6)+   ADC_DATA(6)-
                           ADC_DATA(7)+   ADC_DATA(7)-
                           ADC_DATA(8)+   ADC_DATA(8)-
                           ADC_DATA(9)+   ADC_DATA(9)-
                           ADC_DATA(10)+   ADC_DATA(10)-
                           ADC_DATA(11)+   ADC_DATA(11)-
                           ADC_DATA(12)+   ADC_DATA(12)-
                           ADC_DATA(13)+   ADC_DATA(13)-
                           ADC_DATA(14)+   ADC_DATA(14)-
                           ADC_DATA(15)+   ADC_DATA(15)-
                           CLKA_N   CLKA_P
                           CLKB_N   CLKB_P
                           CLKC_N   CLKC_P
                           CLKD_N   CLKD_P
                           CLKE_N   CLKE_P
                           CLKF_N   CLKF_P
                           CLKG_N   CLKG_P
                           CLKH_N   CLKH_P
                           120MHz+   120MHz-
                           
Percent Routed  ................ 21.46 %

Netline Length  ................ 3,186.86 (in)
Netline Manhattan Length  ...... 3,940.09 (in)
Total Trace Length  ............ 134.45 (in)

Trace Widths Used (th)  ........ 5, 6, 7.87, 8, 10
Vias  .......................... 4163
Via Span  Name                   Quantity
   1-16   025VIA                 1
          018VIA_8               763
          025VIA_10              583
          035VIA                 229
          018VIA_8_14mask-bga    2512
   1-8    025VIA                 30
          020VIA_10              1
          VIA020_010             2
          025VIA_10              20
   9-16   025VIA                 4
          025VIA_10              18

Teardrops....................... 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 1238
    Parts Mounted on Top  ...... 501
        SMD  ................... 483
        Through  ............... 18
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 737
        SMD  ................... 733
        Through  ............... 4
        Test Points  ........... 0
        Mechanical  ............ 0
    Edge Connector Parts  ...... 0

Parts not Placed  .............. 182

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 4439
    Holes per Board Area  ...... 22.38 Holes/Sq. (in)