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Expedition PCB - Pinnacle - Version PCB2004_040223.1326 2004
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Job Directory:        C:\06_JOB_ISR4\CERN_PROTOTYPE\PCB\

Design Status Report: C:\06_JOB_ISR4\CERN_PROTOTYPE\PCB\LogFiles\DesignStatus_41.txt

Wed Dec 13 14:28:22 2006

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DESIGN STATUS
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Board Size Extents  ............ 16.63 X 11.93 (in)
Route Border Extents  .......... 6.25 X 7.64 (in)
Actual Board Area  ............. 198.32 (in)
Actual Route Area  ............. 47.72 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    396.65 Sq. (in)   37.97 Sq. (in)    9.57 %
           Room:                 57.35 Sq. (in)    0 Sq. (in)        0.00 %

Pins  .......................... 7954
Pins per Route Area  ........... 166.68 Pins/Sq. (in)

Layers  ........................ 16
    Layer 1 is a signal layer
        Trace Widths  .......... 5, 6, 7.87, 8, 10
    Layer 2 is a signal layer
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... 5
    Layer 4 is a Positive Plane Layer with nets
        +1.5V
        Trace Widths  .......... None.
    Layer 5 is a signal layer
        Trace Widths  .......... None.
    Layer 6 is a signal layer
        Trace Widths  .......... None.
    Layer 7 is a signal layer
        Trace Widths  .......... None.
    Layer 8 is a signal layer
        Trace Widths  .......... None.
    Layer 9 is a signal layer
        Trace Widths  .......... None.
    Layer 10 is a signal layer
        Trace Widths  .......... None.
    Layer 11 is a signal layer
        Trace Widths  .......... None.
    Layer 12 is a signal layer
        Trace Widths  .......... None.
    Layer 13 is a Positive Plane Layer with nets
        +2.5V
        Trace Widths  .......... None.
    Layer 14 is a signal layer
        Trace Widths  .......... 5
    Layer 15 is a signal layer
        Trace Widths  .......... None.
    Layer 16 is a signal layer
        Trace Widths  .......... 5, 6, 10

Nets  .......................... 1799
Connections  ................... 5541
Open Connections  .............. 4662
Differential Pairs  ............ 25
Differential Pair Names:   ADC_DATA(0)+   ADC_DATA(0)-
                           ADC_DATA(1)+   ADC_DATA(1)-
                           ADC_DATA(2)+   ADC_DATA(2)-
                           ADC_DATA(3)+   ADC_DATA(3)-
                           ADC_DATA(4)+   ADC_DATA(4)-
                           ADC_DATA(5)+   ADC_DATA(5)-
                           ADC_DATA(6)+   ADC_DATA(6)-
                           ADC_DATA(7)+   ADC_DATA(7)-
                           ADC_DATA(8)+   ADC_DATA(8)-
                           ADC_DATA(9)+   ADC_DATA(9)-
                           ADC_DATA(10)+   ADC_DATA(10)-
                           ADC_DATA(11)+   ADC_DATA(11)-
                           ADC_DATA(12)+   ADC_DATA(12)-
                           ADC_DATA(13)+   ADC_DATA(13)-
                           ADC_DATA(14)+   ADC_DATA(14)-
                           ADC_DATA(15)+   ADC_DATA(15)-
                           diffclka+   diffclka-
                           diffclkb+   diffclkb-
                           diffclkc+   diffclkc-
                           diffclkd+   diffclkd-
                           diffclke+   diffclke-
                           diffclkf+   diffclkf-
                           diffclkg+   diffclkg-
                           diffclkh+   diffclkh-
                           120MHz+   120MHz-
                           
Percent Routed  ................ 15.88 %

Netline Length  ................ 3,175.84 (in)
Netline Manhattan Length  ...... 3,934.59 (in)
Total Trace Length  ............ 129.26 (in)

Trace Widths Used (th)  ........ 5, 6, 7.87, 8, 10
Vias  .......................... 3981
Via Span  Name                   Quantity
   1-16   025VIA                 2
          018VIA_8               763
          025VIA_10              955
          035VIA                 229
          020VIA_10              1982
   1-8    020VIA_10              7
          025VIA                 31
   9-16   025VIA                 12

Teardrops....................... 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 1250
    Parts Mounted on Top  ...... 482
        SMD  ................... 464
        Through  ............... 18
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 768
        SMD  ................... 764
        Through  ............... 4
        Test Points  ........... 0
        Mechanical  ............ 0
    Edge Connector Parts  ...... 0

Parts not Placed  .............. 1

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 4282
    Holes per Board Area  ...... 21.59 Holes/Sq. (in)