======================================================================= Expedition PCB - Pinnacle - Version PCB2004_040223.1326 2004 ======================================================================= Job Directory: C:\06_JOB_ISR4\CERN_PROTOTYPE_RTSP\PCB\ Design Status Report: C:\06_JOB_ISR4\CERN_PROTOTYPE_RTSP\PCB\LogFiles\DesignStatus_40.txt Tue Nov 28 11:11:52 2006 ======================================================================= DESIGN STATUS ======================================================================= Board Size Extents ............ 16.63 X 11.93 (in) Route Border Extents .......... 6.25 X 7.64 (in) Actual Board Area ............. 198.32 (in) Actual Route Area ............. 47.72 (in) Placement Areas: Name Available Required Required/Available Entire Board 396.65 Sq. (in) 51.09 Sq. (in) 12.88 % Room: 57.35 Sq. (in) 0 Sq. (in) 0.00 % Pins .......................... 7954 Pins per Route Area ........... 166.68 Pins/Sq. (in) Layers ........................ 16 Layer 1 is a signal layer Trace Widths .......... 5, 6, 7.87, 8 Layer 2 is a signal layer Trace Widths .......... None. Layer 3 is a signal layer Trace Widths .......... 5 Layer 4 is a Positive Plane Layer with nets +1.5V Trace Widths .......... None. Layer 5 is a signal layer Trace Widths .......... None. Layer 6 is a signal layer Trace Widths .......... None. Layer 7 is a signal layer Trace Widths .......... None. Layer 8 is a signal layer Trace Widths .......... None. Layer 9 is a signal layer Trace Widths .......... None. Layer 10 is a signal layer Trace Widths .......... None. Layer 11 is a signal layer Trace Widths .......... None. Layer 12 is a signal layer Trace Widths .......... None. Layer 13 is a Positive Plane Layer with nets +2.5V Trace Widths .......... None. Layer 14 is a signal layer Trace Widths .......... 5 Layer 15 is a signal layer Trace Widths .......... None. Layer 16 is a signal layer Trace Widths .......... 5, 6 Nets .......................... 1783 Connections ................... 5542 Open Connections .............. 4878 Differential Pairs ............ 25 Differential Pair Names: ADC_DATA(0)+ ADC_DATA(0)- ADC_DATA(1)+ ADC_DATA(1)- ADC_DATA(2)+ ADC_DATA(2)- ADC_DATA(3)+ ADC_DATA(3)- ADC_DATA(4)+ ADC_DATA(4)- ADC_DATA(5)+ ADC_DATA(5)- ADC_DATA(6)+ ADC_DATA(6)- ADC_DATA(7)+ ADC_DATA(7)- ADC_DATA(8)+ ADC_DATA(8)- ADC_DATA(9)+ ADC_DATA(9)- ADC_DATA(10)+ ADC_DATA(10)- ADC_DATA(11)+ ADC_DATA(11)- ADC_DATA(12)+ ADC_DATA(12)- ADC_DATA(13)+ ADC_DATA(13)- ADC_DATA(14)+ ADC_DATA(14)- ADC_DATA(15)+ ADC_DATA(15)- diffclka+ diffclka- diffclkb+ diffclkb- diffclkc+ diffclkc- diffclkd+ diffclkd- diffclke+ diffclke- diffclkf+ diffclkf- diffclkg+ diffclkg- diffclkh+ diffclkh- 120MHz+ 120MHz- Percent Routed ................ 11.98 % Netline Length ................ 3,179.46 (in) Netline Manhattan Length ...... 3,909.37 (in) Total Trace Length ............ 122.27 (in) Trace Widths Used (th) ........ 5, 6, 7.87, 8 Vias .......................... 4128 Via Span Name Quantity 1-16 020VIA_10 624 018VIA_8 3267 035VIA 229 1-8 025VIA 1 9-16 025VIA 7 Teardrops....................... 0 Breakouts....................... 0 Virtual Pins.................... 0 Guide Pins ..................... 0 Parts Placed .................. 1257 Parts Mounted on Top ...... 713 SMD ................... 695 Through ............... 18 Test Points ........... 0 Mechanical ............ 0 Parts Mounted on Bottom ... 544 SMD ................... 540 Through ............... 4 Test Points ........... 0 Mechanical ............ 0 Edge Connector Parts ...... 0 Parts not Placed .............. 0 Nested Cells .................. 0 Jumpers ....................... 0 Through Holes ................. 4471 Holes per Board Area ...... 22.54 Holes/Sq. (in)