======================================================================= Expedition PCB - Pinnacle - Version PCB2004_040223.1326 2004 ======================================================================= Job Directory: C:\06_JOB_ISR4\CERN_PROTOTYPE_RTSP\PCB\ Design Status Report: C:\06_JOB_ISR4\CERN_PROTOTYPE_RTSP\PCB\LogFiles\DesignStatus_38.txt Wed Nov 22 10:29:59 2006 ======================================================================= DESIGN STATUS ======================================================================= Board Size Extents ............ 6.3 X 7.69 (in) Route Border Extents .......... 6.25 X 7.64 (in) Actual Board Area ............. 48.42 (in) Actual Route Area ............. 47.72 (in) Placement Areas: Name Available Required Required/Available Entire Board 96.83 Sq. (in) 51.35 Sq. (in) 53.03 % Room: 57.35 Sq. (in) 0 Sq. (in) 0.00 % Pins .......................... 7978 Pins per Route Area ........... 167.18 Pins/Sq. (in) Layers ........................ 16 Layer 1 is a signal layer Trace Widths .......... 7.87, 8 Layer 2 is a signal layer Trace Widths .......... None. Layer 3 is a signal layer Trace Widths .......... None. Layer 4 is a Positive Plane Layer with nets +1.5V Trace Widths .......... None. Layer 5 is a signal layer Trace Widths .......... None. Layer 6 is a signal layer Trace Widths .......... None. Layer 7 is a signal layer Trace Widths .......... None. Layer 8 is a signal layer Trace Widths .......... None. Layer 9 is a signal layer Trace Widths .......... None. Layer 10 is a signal layer Trace Widths .......... None. Layer 11 is a signal layer Trace Widths .......... None. Layer 12 is a signal layer Trace Widths .......... None. Layer 13 is a Positive Plane Layer with nets +2.5V Trace Widths .......... None. Layer 14 is a signal layer Trace Widths .......... None. Layer 15 is a signal layer Trace Widths .......... None. Layer 16 is a signal layer Trace Widths .......... None. Nets .......................... 1803 Connections ................... 5511 Open Connections .............. 4858 Differential Pairs ............ 25 Differential Pair Names: ADC_DATA(0)+ ADC_DATA(0)- ADC_DATA(1)+ ADC_DATA(1)- ADC_DATA(2)+ ADC_DATA(2)- ADC_DATA(3)+ ADC_DATA(3)- ADC_DATA(4)+ ADC_DATA(4)- ADC_DATA(5)+ ADC_DATA(5)- ADC_DATA(6)+ ADC_DATA(6)- ADC_DATA(7)+ ADC_DATA(7)- ADC_DATA(8)+ ADC_DATA(8)- ADC_DATA(9)+ ADC_DATA(9)- ADC_DATA(10)+ ADC_DATA(10)- ADC_DATA(11)+ ADC_DATA(11)- ADC_DATA(12)+ ADC_DATA(12)- ADC_DATA(13)+ ADC_DATA(13)- ADC_DATA(14)+ ADC_DATA(14)- ADC_DATA(15)+ ADC_DATA(15)- diffclka+ diffclka- diffclkb+ diffclkb- diffclkc+ diffclkc- diffclkd+ diffclkd- diffclke+ diffclke- diffclkf+ diffclkf- diffclkg+ diffclkg- diffclkh+ diffclkh- 120MHz+ 120MHz- Percent Routed ................ 11.85 % Netline Length ................ 3,770.81 (in) Netline Manhattan Length ...... 4,683.25 (in) Total Trace Length ............ 115.85 (in) Trace Widths Used (th) ........ 7.87, 8 Vias .......................... 4120 Via Span Name Quantity 1-16 035VIA 229 020VIA_10 624 018VIA_8 3267 Teardrops....................... 0 Breakouts....................... 0 Virtual Pins.................... 0 Guide Pins ..................... 0 Parts Placed .................. 1250 Parts Mounted on Top ...... 1010 SMD ................... 988 Through ............... 22 Test Points ........... 0 Mechanical ............ 0 Parts Mounted on Bottom ... 240 SMD ................... 240 Through ............... 0 Test Points ........... 0 Mechanical ............ 0 Edge Connector Parts ...... 0 Parts not Placed .............. 12 Nested Cells .................. 0 Jumpers ....................... 0 Through Holes ................. 4471 Holes per Board Area ...... 92.34 Holes/Sq. (in)