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Expedition PCB - Pinnacle - Version PCB2004_040223.1326 2004
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Job Directory:        C:\06_JOB_ISR4\CERN_PROTOTYPE_RTSP\PCB\

Design Status Report: C:\06_JOB_ISR4\CERN_PROTOTYPE_RTSP\PCB\LogFiles\DesignStatus_23.txt

Fri Nov 17 10:42:24 2006

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DESIGN STATUS
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Board Size Extents  ............ 6.3 X 7.69 (in)
Route Border Extents  .......... 6.25 X 7.64 (in)
Actual Board Area  ............. 48.42 (in)
Actual Route Area  ............. 47.72 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    96.83 Sq. (in)    49.45 Sq. (in)    51.07 %
           Room:                 57.35 Sq. (in)    0 Sq. (in)        0.00 %

Pins  .......................... 7787
Pins per Route Area  ........... 163.18 Pins/Sq. (in)

Layers  ........................ 16
    Layer 1 is a signal layer
        Trace Widths  .......... 7.87, 8
    Layer 2 is a signal layer
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... None.
    Layer 4 is a Positive Plane Layer with nets
        +1.5V
        Trace Widths  .......... None.
    Layer 5 is a signal layer
        Trace Widths  .......... None.
    Layer 6 is a signal layer
        Trace Widths  .......... None.
    Layer 7 is a signal layer
        Trace Widths  .......... None.
    Layer 8 is a signal layer
        Trace Widths  .......... None.
    Layer 9 is a signal layer
        Trace Widths  .......... None.
    Layer 10 is a signal layer
        Trace Widths  .......... None.
    Layer 11 is a signal layer
        Trace Widths  .......... None.
    Layer 12 is a signal layer
        Trace Widths  .......... None.
    Layer 13 is a Positive Plane Layer with nets
        +2.5V
        Trace Widths  .......... None.
    Layer 14 is a signal layer
        Trace Widths  .......... None.
    Layer 15 is a signal layer
        Trace Widths  .......... None.
    Layer 16 is a signal layer
        Trace Widths  .......... None.

Nets  .......................... 1772
Connections  ................... 2041
Open Connections  .............. 1993
Differential Pairs  ............ 0
Percent Routed  ................ 2.35 %

Netline Length  ................ 1,476.23 (in)
Netline Manhattan Length  ...... 1,913.26 (in)
Total Trace Length  ............ 81.67 (in)

Trace Widths Used (th)  ........ 7.87, 8
Vias  .......................... 2972
Via Span  Name                   Quantity
   1-16   018VIA_8               2119
          020VIA_10              624
          035VIA                 229

Teardrops....................... 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 166
    Parts Mounted on Top  ...... 166
        SMD  ................... 152
        Through  ............... 14
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 0
        SMD  ................... 0
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Edge Connector Parts  ...... 0

Parts not Placed  .............. 921

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 3312
    Holes per Board Area  ...... 68.41 Holes/Sq. (in)