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Expedition PCB - Pinnacle - Version PCB2004_040223.1326 2004
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Job Directory:        C:\02_job_tom\MRM_SVIM\PCB\

Design Status Report: C:\02_job_tom\MRM_SVIM\PCB\LogFiles\DesignStatus_01.txt

Wed Aug 23 13:42:22 2006

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DESIGN STATUS
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Board Size Extents  ............ 6.3 X 7.68 (in)
Route Border Extents  .......... 6.25 X 7.62 (in)
Actual Board Area  ............. 48.38 (in)
Actual Route Area  ............. 47.31 (in)

Placement Areas: Name            Available         Required          Required/Available
                 Entire Board    96.77 Sq. (in)    87.26 Sq. (in)    90.17 %
           Room:                 57.35 Sq. (in)    0 Sq. (in)        0.00 %

Pins  .......................... 5191
Pins per Route Area  ........... 109.72 Pins/Sq. (in)

Layers  ........................ 14
    Layer 1 is a signal layer
        Trace Widths  .......... None.
    Layer 2 is a signal layer
        Trace Widths  .......... None.
    Layer 3 is a signal layer
        Trace Widths  .......... None.
    Layer 4 is a signal layer
        Trace Widths  .......... None.
    Layer 5 is a signal layer
        Trace Widths  .......... None.
    Layer 6 is a signal layer
        Trace Widths  .......... None.
    Layer 7 is a signal layer
        Trace Widths  .......... None.
    Layer 8 is a signal layer
        Trace Widths  .......... None.
    Layer 9 is a signal layer
        Trace Widths  .......... None.
    Layer 10 is a signal layer
        Trace Widths  .......... None.
    Layer 11 is a signal layer
        Trace Widths  .......... None.
    Layer 12 is a signal layer
        Trace Widths  .......... None.
    Layer 13 is a signal layer
        Trace Widths  .......... None.
    Layer 14 is a signal layer
        Trace Widths  .......... None.

Nets  .......................... 964
Connections  ................... 1777
Open Connections  .............. 1777
Differential Pairs  ............ 0
Percent Routed  ................ 0.00 %

Netline Length  ................ 1,946.35 (in)
Netline Manhattan Length  ...... 2,148.32 (in)
Total Trace Length  ............ 0 (in)

Trace Widths Used (th)  ........ None.
Vias  .......................... 0

Teardrops....................... 0
Breakouts....................... 0

Virtual Pins.................... 0
Guide Pins ..................... 0

Parts Placed  .................. 23
    Parts Mounted on Top  ...... 19
        SMD  ................... 15
        Through  ............... 4
        Test Points  ........... 0
        Mechanical  ............ 0
    Parts Mounted on Bottom  ... 4
        SMD  ................... 4
        Through  ............... 0
        Test Points  ........... 0
        Mechanical  ............ 0
    Edge Connector Parts  ...... 0

Parts not Placed  .............. 809

Nested Cells  .................. 0

Jumpers  ....................... 0

Through Holes  ................. 384
    Holes per Board Area  ...... 7.94 Holes/Sq. (in)