MVD FEE / DCM Data Formats

J.Nagle and C.Y. Chi created 5-22-98

updated 7/14/98

SS.Ryu and J.P.Sullivan 8-Feb-2000

The following document is meant to review the data format for the Multiplicity Vertex Detector (MVD), as:

    1. output from the FEE to the DCM
    2. output from the DCM in pass-through mode

Most of these formats are already specified and are presented here for verification.

This format document is only concerned with these data packet formats, and does not discuss packet headers, frame headers or other possible data packet formats for the MVD. It is possible in the future to consider further alternate formats produced in the signal processors (SHARC DSP’s) of the DCM’s.

(1) Output from the FEE to the DCM

Below is the format as sent from the MVD FEE (i.e. out of the DCIM) over fiber to the DCM. The data is sent in 16-bit words (with additional CAV and DAV control lines).

There is a normal (known in the MVD group as correlated mode) and alternate (known in the MVD group as raw mode) FEM formats for the MVD. Below we just present the normal format (which is more compact).

Sequence Number

16-bit word format

CAV

DAV

Comments

1

0xFFFF (all bits on)

1

0

 

2

Detector ID

0

1

=2 for MVD

3

Event Number

0

1

L1 accept no., 10 bits only

4

Module Address

0

1

6 bits, set by DCIM jumpers

5

Flag Word

0

1

* important specs…

6

FEM Beam Clock Counter (8 bits)

0

1

Least significant bits

7

First Data Word (lowest 10 bits used)

0

1

*see table below

.

.

.

.

.

0

0

0

1

1

1

 

263

Last Data Word (lowest 10 bits used)

0

1

 

264

User Word 1

0

1

location of 1st parity error

265

User Word 2

0

1

 

266

User Word 3

0

1

 

267

User Word 4

0

1

 

268

User Word 5

0

1

 

269

User Word 6

0

1

 

270

User Word 7

0

1

location of 7th parity error

271

User Word 8

0

1

misc flags, typical: 400 or 4400 (hex)

272

Vertical Parity Word

0

1

 

273

0x0000 (all bits off)

1

0

 

*Note that sub-systems can use up to a maximum of eight user words, and the MVD has used all of these words.

The data words are from 256 channels with just one data word per channel). There is an additional word for the AMU cell number. Thus the total number of data words is = 256 X 1 + 1 = 257. All data words are only 10 bits.

Data

Sequence

Channel Number

16-bit Format

Comments

0

X

AMU Cell Numbers

NNMM, NN=post-sample cell, MM=pre-sample

1

1

Channel 1 Qpost-Qpre

Bit 9-0 (data)

2

1

Channel 2 Qpost-Qpre

"

.

.

.

.

.

.

 

.

.

.

255

255

Channel 255 Qpost-Qpre

"

256

256

Channel 256 Qpost-Qpre

"

 

 

(2) Output from DCM in pass-through mode

If the DCM is in pass-through mode (no zero suppression), the data still passes through an FPGA and is reformatted before going into the on-board DSP. All data is transferred into the DSP in 32-bit words.

Sequence Number

Bit 31

Bits 30-28

Bits 27-16

Bits 15-0

1

1

0

15

Detector ID=2 for MVD

2

1

0

6

Level-1 event counter

3

1

0

6

DCIM address (6 bits)

4

1

0

6

Flag word

5

1

0

6

Beam clock counter

0

0

0

0

AMU Cell #s

1

0

0

1

Ch 1 Qpost-Qpre

2

0

0

2

Ch 2 Qpost-Qpre

.

.

.

.

 

.

.

.

.

256

0

0

256

Ch 256 Qpost-Qpre

1

1

1

14

User Word 1

2

1

2

14

User Word 2

3

1

3

14

User Word 3

4

1

4

14

User Word 4

5

1

5

14

User Word 5

6

1

6

14

User Word 6

7

1

7

14

User Word 7

8

1

0

14

User Word 8

9

1

1

15

Parity Word

10

1

2

15

Last Word

The sequence numbers listed on the left column are not included in the data stream, just the 32-bit word sequence. In this mode, the number of words in the packet is of fixed length. The total packet length is = 5 + 1 + 256 + 10 = 272.

It should be noted that the definitions for the upper bits (16-31) are not yet finalized. Final definitions are contingent on revision of DCM FPGA coding.

  1. DCM output in zero-suppression mode

With zero-suppression the data packet is no longer of fixed length. Single words are either kept or removed, but otherwise the format is the same as above.

The notes from Chi indicate that the zero suppression will go as:

(Qpost(ch) - Qpre(ch)) < Theshold(ch)