qin1-32 -	Charge inputs from the detectors.
vout1-32 -	Voltage outputs from preamplifier channels.
calibrate_bar -	Normally low. After calibration pattern is loaded, pin is changed to high for pre-charge and then low for actual calibration voltage output.
pre_bias -	Output of preamplifier bias point. Needs to have filter capacitor (1uF).
pre_reset -	Preamplifier reset. Normally low. Reset occurs when high.
s2_reset -	Stage 2 reset. Normally low. Reset occurs when high.
s2_bias -	Output of stage 2 bias point. Needs to have filter capacitor (1uF).
discbias_1 -	Discriminator bias output.
discbias_2 -	Discriminator bias output.
ibias -	Current output bias point.
idiscout -	Multiplicity current output. Approx. 50mA/channel.
readback_en -	Normally low. After data is loaded, this line is forced high for one full sclk pulse. The line is then forced low. The readback is then accomplished by continuously pulsing sclk.
reset -	Normally low. Master shift-logic reset when high.
sdout -	Output of serial string stored data.
vcal -	Monitor point of calibration voltage.
vgate -	Monitor point for discriminator gate voltage.
vfb_res -	Monitor point for preamplifier feedback resistor control voltage.
sdin -	Input for serial string data.
dac_bias -	Output of dac bias point.
dac_vmid -	2.5 volt input for dac bias.
disc_vmid -	Monitor point for discriminator midpoint voltage.
ithresh -	Monitor point for discriminator threshold bias.
dclk -	Normally low. Positive edge clocks serial data into data registers.
sclk -	Normally low. Positive edge clocks serial data into shift registers.
dac_amp_bias1 -	Bias point output for vcal and vfb_res dacs.
dac_amp_bias2 -	Bias point output for vgate and disc_vmid, and ithresh dacs.

vdd_dig -	Digital +5V.
vss_dig -	Digital GND.
vdd_pre -	Preamplifier and detector return +5V.
vss_pre -	Preamplifier GND.
vdd_post -	2nd stage, discriminator, and pad frame +5V.
vss_post -	2nd stage, discriminator, and pad frame GND.