GENERAL DESCRIPTION

The PHENIX Multiplicity Vertex Detector (MVD) is a 35,000 channel device comprised of two layers of silicon strip detectors in the central barrel (112 detectors total) and two disk-shaped endcaps. Each endcap is formed by an assembly of 12, 30° wedge-shaped silicon pad detectors. The main task of the MVD is to provide a multiplicity measurement to the level-1 trigger and to measure fluctuations within the multiplicity distribution on an event-by-event basis. The detector has full azimuthal coverage and is capable of reconstructing the collision vertex to roughly 2mm.

SILICON STRIP DETECTORS

GEOMETRY

The inner and outer strip detectors are identical, except in length. The outer strip detector dimensions are 74.5 x 53 mm, and the inner strip detectors are 52 x 53 mm. Both are fabricated on 4" wafers. Each detector is comprised of 256 individual p-type strips on an n-type substrate. At the readout end of the detector there is a 2.3 x 53 mm area of inactive silicon, intended as a glue area for a kapton readout cable. The area of each outer strip is 71.5 x 0.05 mm. The area of each inner strip is 49 x 0.05 mm. The strip pitch in both cases is 200 micro-m. The total thickness of the detectors is 300 micro-m +/- 15 micro-m.

AC COUPLING

The detectors have integrated ac-coupling. The entire area of the strip is covered by a 200 nm oxide layer. On top of the oxide, aluminum is deposited along the entire length of the strip. The aluminization is 40 microns wide, centered on the 50 micron wide p-implant. The strip-oxide-aluminum structure forms a 200 pF coupling capacitor. The strips are terminated at the readout end of the detector in 80 x 200 micro-m bond pads. There are spy pads at the oppositite end of the detector which allow for probing the implant directly to perform dc characterization of the detector.

BIAS

Each strip is individually biased through a polysilicon resistor. The resistor is a meander structure that is deposited on the junction side of the detector between a common bias line and the strips. The initial specification for the value of these resistors was 5 M-Ohms, +/- 1 M-Ohms. The vendor has had some difficulty meeting this spec, so we have since relaxed the specification to read 4 to 11 M-Ohms.

GUARD RINGS

Each detector has two peripheral guard rings. The rings are aluminized p-implants, 50 microns wide. The inner guard ring surrounds the strips, and is placed between the strips and the bias line. The outer guard ring is place between the bias line and the cut-edge of the detector, and it also covers the periphery of the detector. The guard rings can be biased either independently, or run together at the same potential. The nominal operating condition is to run the inner guard ring at the strip reference potential, and leave the outer guard floating.

TEST STRUCTURES and DC CHARACTERIZATION

Various test structures are fabricated on the wafer, outside of the active region of the detector to facilitate the dc characterization of the detectors. We estimate the depletion voltage of the detector by making a capacitance vs voltage measurement on a 1 x 1 cm test diode. We measure the capacitance at 10, 100, and 1000 kHz at incremental voltage steps up to 60V. A program that is written in Labview controls the operation. The output is written to a file and stored in a data base for future reference. Plotting this distribution reveals two linear slopes in the capacitance values. The voltage where these slopes intersect gives a good approximation of the full depletion voltage of the detector.

We have the foundry deposit additional polysilicon structures below the active region of the detector, in alignment with exery 16th strip on the detector. We measure the values of these test resistors to determine the absolute value, as well as the uniformity of resistance across the detector. This measurement is done by hand with two manual probes and recorded in a log. The information is then transferred to a data base.

Capacitor test structures are tested for breakdown up to 100 V.

We use a 32-channel needle probe card on a manual probe station to measure individual leakage current in the strips. The card is output through a switching mainframe to a picoamp meter, which is also a voltage source. A program that is written in Labview controls the source/meter to make a sequential current reading on each of the 32 channels at incremental voltage steps, up to a maximum of 100V. These data are written to files and stored in a data base for future reference.

We use the same 32 channel probe card to look for shorts between the metal and the strip implant. We probe the bond pads and look for leakage current while applying bias voltage to the detector. If the coupling oxide is good, no leakage current is measured. On the other hand, the presence of a leakage current indicates that there is a rupture in the oxide that has been filled with metal during the aluminzation, and has shorted to the strip.

AC CHARACTERIZATION

The detector response is tested using a 1064 nm focused laser diode, implemented on an x/y stage. The laser spot can be focused to roughly 30 micro-m. This is sufficiently small to probe the 150 micro-m non-metallized region in the gap between adjacent strips. Beta radiation sources are also used to examine the detector response. Two strip detector prototypes were also tested at the AGS in the test beamline to measure the detector response to minimum ionizing particles in an accelerator environment.

TECHNICAL SPECIFICATIONS STRIPS

Resistivity, 5-8 k-Ohms
Thickness 300 micro-m +/- 15 micro-m
Strip pitch, 200 micro-m
Implant width, 50 micro-m
Metallization width, 40 micro-m
Total leakage current at full depletion, < 1 micro-A per detector (room temperature)
Individual strip leakage current at full depletion, 1 nA typical, no individual strip > 50 nA (room temperature)
Full depletion voltage, 30-50 V
Breakdown voltage, 2 x full depletion
Coupling oxide, 200 nm
Capcitor breakdown voltage, 2 x full depletion

Polysilicon resistor uniformity, 4-11 M-Ohms
Minimum acceptance level, 99% (3 faults)

SILICON PAD DETECTORS

GEOMETRY

The pad detectors are 30° wedges. Twelve detectors assembled together form a complete disk which is mounted on each endcap of the MVD. The detectors are fabricated on 4" wafers with p-type implantation on an n-type substrate. The radial height of the detector is 70 mm. The width of the detector at the outer radius is 64 mm and 24 mm at the inner radius. The pads are arranged in 12 columns by 21 rows, for a total of 252 pad elements per detector. The road between adjacent columns is 200 mm and the road between adjacent rows is 300 micro-m. The larger road is to accomodate the bias resistors. The area of pads within a given row scale with their radial location, and therefore with the expected angular-dependent particle rate. The pads at the inner radius are 2 x 2 mm. The pads at the outer radius are 4.5 x 4.5 mm. The pad geometry was fabricated in both a single-metal and a double-metal process. The single-metal design is a simple detector to produce, but requires an additional kapton router to get the signals from the individual pads to the outer radius of the detector where the front-end electronics are located. The double-metal detector has this feature integrated into the detector fabrication process. The trace-router metal in this design is separated from metal one by a 4 micro-m thick layer of silicon dioxide. Lab tests have been performed on prototypes of both designs, and the double-metal process has been chosen for the MVD. It requires less handling for assembly, has an inherently better ordered readout with respect to the physical pad locations, is more strightforward to probe, and does not exhibit a significantly greater level of crosstalk due to the overlapping metal layers. Therefore, only the double-metal detector will be described in greater detail.

AC COUPLING

Each pad is ac coupled. A 200 nm silicon dioxide layer covers the implant area, and a large percentage of that area is aluminized. As with the strips, the pad-silicon dioxide-metal sandwich forms the capacitor. Spy pads are opened in the non-metallized area to allow for direct probing of the pad.

BIAS

Each pad is individually biased through a polysilicon resistor. The specifications for the resistor value is identical to that for the strips; 4 - 11 M-Ohms. The common bias line is routed down each side of the detector, adjacent to the outer two columns. The bias resistors are located in every other row of the detector, connecting either to a pad located above or below that row.

METAL TWO

The second metal layer is the trace routing layer which routes the pad outputs to bond pads, located at the outer radius of the detector. The traces are 16 micro-m wide on 150 micro-m pitch. They terminate in a double row of 80 x 200 micro-m bond pads.

GUARD RINGS

As with the strip detectors, there is both an inner and an outer guard ring surrounding the periphery of the pad detector. The inner guard is 50 micro-m from the pad at the closest approach and 100 micro-m at the farthest approach. The outer guard is located between the bias line and the cut-edge of the detector.

TEST STRUCTURES and DC CHARACTERIZATION

As with the strip detectors, various test structures are fabricated on the wafer, outside of the active region of the detector to facilitate the dc characterization of the detectors.

The depletion voltage of the pad detector is estimated by running a C/V curve on a test diode, identical to the method used for the strip detectors. These data are recorded in a data base.

Polysilicon resistor test structures are deposited around the periphery of the pad detector. These are measured for their absolute value and to give an indication of the quality of uniformity of the resistance across the detector. The data are recorded and put into a data base.

A test pad in the smallest, and in the largest geometry is fabricated adjacent to the detector. We run C/V plots on these structures.

Unlike the strips, the spy pad locations for the pads are not located in a geometry that allows for the use of a multi-pin probe card. Therefore, each pad I/V is measured by hand, one at a time. These data are logged and then entered into a data base.

The probe card is used to check for shorts by probing the bond pads at the outside edge of the detector.

AC CHARACTERIZATION

The detector response is tested using a 1064 nm focused laser diode, implemented on an x/y stage. The laser spot can be focused to roughly 30 micro-m. This is sufficiently small to probe the roads in the non-metallized region in the column and row gaps between adjacent pads. Beta radiation sources are also used to examine the detector response.

TECHNICAL SPECIFICATIONS PADS

Resistivity, 5-8 k-Ohms
Thickness 300 micro-m +/- 15 micro-m
Pad area, 2 x 2 mm inner radius to 4.5 x 4.5 mm outer radius
Road between adjacent columns, 200 micro-m
Road between adjacent rows, 300 micro-m
Metal one-to-two separation, 4 micro-m silicon dioxide
Total leakage current at full depletion, < 1 micro-A per detector (room temperature)
Individual strip leakage current at full depletion, 1 nA to 2 nA typical, no individual strip > 50 nA (room temperature)
Full depletion voltage, 30-50 V
Breakdown voltage, 2 x full depletion
Coupling oxide, 200 nm
Capcitor breakdown voltage, 2 x full depletion

Polysilicon resistor uniformity, 4-11 M-Ohms
Minimum acceptance level, 99% (3 faults)