On 6-Aug-99 it was tested again with the latest Xilinx programs (mcmc6.hex and mcmr8.hex). The results were the same for blocks 7 and 8. I did not check the serial readback. Numerous DACs were adjusted in an effort to fix both of these problems. None of them fixed the problems. Details are given on pages 54-55 of the logbook.

The 7th block of channels always returns overflow (3FF). The DACs which control the ramp were adjusted over their full range (Iref from 2 to 70 and Vref from 0.2 to 4.8). The ADCs always returned 3FF. In raw mode, the pre and post samples were both overflow. The preamp spy line responded normally to Vcal input. The AMU spy line (MUX2) did not work on any chip except the 8th chip on this MCM, so I could not check the response there. Changing Vcal did not help. Changed the level-1 delay by one beam clock in each direction did not help. Changing Vfb did not help.

The 8th block of channels seemed to have a lot of noise -- the ADC value fluctuates by 100-200 channels (sigma) for a fixed input charge. Most of the tests were done with bench-cal, but the same result was seen with level-1 triggers. In raw mode, these event-to-event fluctuations were not seen. However, the ADC values did not respond to changes in Vcal and MUX2 stopped working when switched to raw mode.

On 19-Aug-1999 this was tested after replacing surface mount compnents and checking for shorts. Results were the same.

Conclusion: on 6/8 of this MCM works.