// jfrantz Thu May 3 02:08:05 2001updated w/ updateSIDs.pl // Tue Jul 31 18:27:12 2001 updated w/ updateSIDs.pl // Wed Oct 10 18:29:09 2001 updated w/ updateSIDs.pl //------------------------------------------------------- // configuration file for Granule MVD //------------------------------------------------------- // // j.nagle Mar 22, 2001 updated - // JPSullivan May 3, 2001 made packet ID'sconsistent with // http://p25ext.lanl.gov/phenix/mvd/elect/addressing/year2.html // AGHansen Aug 28, 2001 updated to fpga with amucell correction. // Mon Nov 18 2002 update for year-3 configuration (JPSullivan), see: // http://p25ext.lanl.gov/phenix/mvd/elect/addressing/year3.html #include "evb_dcm_common.pcf" #include "Level1DD.pcf" // A) READOUT MODE to be specified by RC at init time // RC must run gmake with -D with one of the following options: // 1) "PAR_JSEB" data to partitioner and then via cable to JSEB on SEB (default) // 2) "PAR_TCPIP" data to partitioner and then over ethernet to SEB // 3) "DSP5_TCPIP" data to DCM dsp5 and then over ethernet to SEB // 4) "DSP14_TCPIP" data to DCM dsp 1-4 and then over ethernet to SEB #ifdef PAR_JSEB label:READOUT_MODE, method:PAR_TO_JSEB #define READOUT_DEFINED #endif #ifdef PAR_TCPIP label:READOUT_MODE, method:PAR_TO_TCPIP #define READOUT_DEFINED #endif #ifdef DSP5_TCPIP label:READOUT_MODE, method:DSP5_TO_TCPIP #define READOUT_DEFINED #endif #ifdef DSP14_TCPIP label:READOUT_MODE, method:DSP14_TO_TCPIP #define READOUT_DEFINED #endif // *** default value of readout #ifndef READOUT_DEFINED label:READOUT_MODE, method:PAR_TO_TCPIP #endif // B) ZERO SUPPRESS or not to be specified by RC at init time // RC must run gmake with -D with one of the following options: // 1) "ZERO" zero suppress (default) hit_format = IDMUTC_FPGA0SUP = 1111 // 2) "NOZERO" no zero suppression hit_format = IDMUTC_FPGA = 1011 #ifdef NORMAL #ifdef ZERO // This is the amucell dependent fpga zero suppressed format #define HIT_FORMAT 1502 #else #define HIT_FORMAT 1002 #endif #endif #ifdef ALTERNATE #ifdef ZERO #define HIT_FORMAT 1302 #else #define HIT_FORMAT 1202 #endif #endif // ** default value of the hit format #ifndef HIT_FORMAT #ifdef ZERO #define HIT_FORMAT 1502 #else #define HIT_FORMAT 1002 #endif #endif // C) There may eventually be other level-2 trigger primitive related options //------------------------------------------------------------------------------- // Extra #defines just for ease of typing #ifndef DCM_DSP_MVD #ifdef FAKE #define DCM_DSP_MVD $DCM_DSP/dsp_fake_fe2_ldr.bin #elif defined(ALTERNATE) #define DCM_DSP_MVD $DCM_DSP/dsp_prog_mvd_ldr.bin.long #else #define DCM_DSP_MVD $DCM_DSP/dsp_prog_mvd_ldr.bin #endif #endif #ifndef DCM_DSP5_MVD #define DCM_DSP5_MVD $DCM_DSP/dsp5_tot_ldr.bin #endif #ifndef DCM_FPGA_MVD #ifdef ALTERNATE #define DCM_FPGA_MVD $DCM_FPGA/phx_dcm_mvd_v2_2smp.rbf #else //#define DCM_FPGA_MVD $DCM_FPGA/phx_dcm_fpga_mvd.rbf // now using new fpga with amucell correction #define DCM_FPGA_MVD $DCM_FPGA/phx_dcm_mvd_v3.rbf #endif #endif #ifndef DCM_LIST_MVD #ifdef ALTERNATE #define DCM_LIST_MVD $DCM_DATA/mvd1202.list #else #define DCM_LIST_MVD $DCM_DATA/mvd1002.list #endif #endif #ifndef DCM_PED_MVD #define DCM_PED_MVD pnull #endif //------------------------------------------------------------------------------- label:ONCS_GTM, name:GTM.MVD, file:$ONLINE_CONFIGURATION/GTM/GTM.MVD.gtm //------------------------------------------------------------------------------- //------------------------------------------------------------------------------- //------------------------------------------------------------------------------- // MVD boards - group a (corresponds to all but the last 8 packets in the inner barrel) label:ONCS_PARTITIONER, name:DCMGROUP.MVD.0, controller:iocondev4b, index:0, file:$ONLINE_CONFIGURATION/Dcm/mvd_a_daq4b_0.dat, SEB_MVD_0 label:ONCS_PAR, name:PAR.MVD.1, parent:DCMGROUP.MVD.0, slot:11 label:ONCS_DCB, name:DCB.MVD.1, parent:DCMGROUP.MVD.0, slot:3, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.11, parent:DCB.MVD.1, type:ONCS_MVD, unit:1, sourceid:1d02, format:HIT_FORMAT, \ multiplex:2, packetid1:2001, packetid2:2002, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2002.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2002.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2001.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2002.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.12, parent:DCB.MVD.1, type:ONCS_MVD, unit:2, sourceid:2d02, format:HIT_FORMAT, \ multiplex:2, packetid1:2003, packetid2:2004, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2003.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2004.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2003.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2004.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.13, parent:DCB.MVD.1, type:ONCS_MVD, unit:3, sourceid:3d02, format:HIT_FORMAT, \ multiplex:2, packetid1:2005, packetid2:2006, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2005.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2006.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2005.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2006.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.14, parent:DCB.MVD.1, type:ONCS_MVD, unit:4, sourceid:4d02, format:HIT_FORMAT, \ multiplex:2, packetid1:2008, packetid2:2007, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2007.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2007.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2008.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2007.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.15, parent:DCB.MVD.1, unit:5, sourceid:5d02, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD //------------------------------------------------------------------------------- label:ONCS_DCB, name:DCB.MVD.2, parent:DCMGROUP.MVD.0, slot:4, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.21, parent:DCB.MVD.2, type:ONCS_MVD, unit:1, sourceid:1d03, format:HIT_FORMAT, \ multiplex:2, packetid1:2010, packetid2:2009, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2010.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2009.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2010.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2009.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.22, parent:DCB.MVD.2, type:ONCS_MVD, unit:2, sourceid:2d03, format:HIT_FORMAT, \ multiplex:2, packetid1:2012, packetid2:2011, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2012.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2011.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2012.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2011.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.23, parent:DCB.MVD.2, type:ONCS_MVD, unit:3, sourceid:3d03, format:HIT_FORMAT, \ multiplex:2, packetid1:2013, packetid2:2014, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2013.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2014.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2013.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2014.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.24, parent:DCB.MVD.2, type:ONCS_MVD, unit:4, sourceid:4d03, format:HIT_FORMAT, \ multiplex:2, packetid1:2015, packetid2:2016, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2015.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2016.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2015.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2016.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.25, parent:DCB.MVD.2, unit:5, sourceid:5d03, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD //------------------------------------------------------------------------------- label:ONCS_DCB, name:DCB.MVD.3, parent:DCMGROUP.MVD.0, slot:5, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.31, parent:DCB.MVD.3, type:ONCS_MVD, unit:1, sourceid:1d04, format:HIT_FORMAT, \ multiplex:2, packetid1:2017, packetid2:2018, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2017.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2018.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2017.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2018.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.32, parent:DCB.MVD.3, type:ONCS_MVD, unit:2, sourceid:2d04, format:HIT_FORMAT, \ multiplex:2, packetid1:2020, packetid2:2019, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2020.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2019.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2020.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2019.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.33, parent:DCB.MVD.3, type:ONCS_MVD, unit:3, sourceid:3d04, format:HIT_FORMAT, \ multiplex:2, packetid1:2022, packetid2:2021, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2022.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2021.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2022.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2021.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.34, parent:DCB.MVD.3, type:ONCS_MVD, unit:4, sourceid:4d04, format:HIT_FORMAT, \ multiplex:2, packetid1:2024, packetid2:2023, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2024.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2023.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2024.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2023.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.35, parent:DCB.MVD.3, unit:5, sourceid:5d04, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD //------------------------------------------------------------------------------- label:ONCS_DCB, name:DCB.MVD.4, parent:DCMGROUP.MVD.0, slot:6, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.41, parent:DCB.MVD.4, type:ONCS_MVD, unit:1, sourceid:1d05, format:HIT_FORMAT, \ multiplex:2, packetid1:2025, packetid2:2026, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2025.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2026.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2025.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2026.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.42, parent:DCB.MVD.4, type:ONCS_MVD, unit:2, sourceid:2d05, format:HIT_FORMAT, \ multiplex:2, packetid1:2027, packetid2:2028, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2027.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2028.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2027.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2028.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.43, parent:DCB.MVD.4, type:ONCS_MVD, unit:3, sourceid:3d05, format:HIT_FORMAT, \ multiplex:2, packetid1:2029, packetid2:2030, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2029.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2030.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2029.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2030.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.44, parent:DCB.MVD.4, type:ONCS_MVD, unit:4, sourceid:4d05, format:HIT_FORMAT, \ multiplex:2, packetid1:2032, packetid2:2031, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2032.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2031.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2032.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2031.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.45, parent:DCB.MVD.4, unit:5, sourceid:5d05, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD //------------------------------------------------------------------------------- label:ONCS_DCB, name:DCB.MVD.5, parent:DCMGROUP.MVD.0, slot:7, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.51, parent:DCB.MVD.5, type:ONCS_MVD, unit:1, sourceid:1d06, format:HIT_FORMAT, \ multiplex:2, packetid1:2034, packetid2:2033, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2034.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2033.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2034.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2033.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.52, parent:DCB.MVD.5, type:ONCS_MVD, unit:2, sourceid:2d06, format:HIT_FORMAT, \ multiplex:2, packetid1:2036, packetid2:2035, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2036.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2035.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2036.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2035.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.53, parent:DCB.MVD.5, type:ONCS_MVD, unit:3, sourceid:3d06, format:HIT_FORMAT, \ multiplex:2, packetid1:2037, packetid2:2038, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2037.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2038.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2037.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2038.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.54, parent:DCB.MVD.5, type:ONCS_MVD, unit:4, sourceid:4d06, format:HIT_FORMAT, \ multiplex:2, packetid1:2039, packetid2:2040, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2039.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2040.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2039.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2040.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.55, parent:DCB.MVD.5, unit:5, sourceid:5d06, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD //------------------------------------------------------------------------------- label:ONCS_DCB, name:DCB.MVD.6, parent:DCMGROUP.MVD.0, slot:8, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.61, parent:DCB.MVD.6, type:ONCS_MVD, unit:1, sourceid:1d07, format:HIT_FORMAT, \ multiplex:2, packetid1:2041, packetid2:2042, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2041.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2042.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2041.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2042.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.62, parent:DCB.MVD.6, type:ONCS_MVD, unit:2, sourceid:2d07, format:HIT_FORMAT, \ multiplex:2, packetid1:2044, packetid2:2043, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2044.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2043.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2044.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2043.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.63, parent:DCB.MVD.6, type:ONCS_MVD, unit:3, sourceid:3d07, format:HIT_FORMAT, \ multiplex:2, packetid1:2046, packetid2:2045, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2046.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2045.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2046.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2045.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.64, parent:DCB.MVD.6, type:ONCS_MVD, unit:4, sourceid:4d07, format:HIT_FORMAT, \ multiplex:2, packetid1:2048, packetid2:2047, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2048.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2047.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2048.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2047.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.65, parent:DCB.MVD.6, unit:5, sourceid:5d07, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD //------------------------------------------------------------------------------- label:ONCS_DCB, name:DCB.MVD.7, parent:DCMGROUP.MVD.0, slot:9, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.71, parent:DCB.MVD.7, type:ONCS_MVD, unit:1, sourceid:1d08, format:HIT_FORMAT, \ multiplex:2, packetid1:2049, packetid2:2050, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2049.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2050.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2049.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2050.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.72, parent:DCB.MVD.7, type:ONCS_MVD, unit:2, sourceid:2d08, format:HIT_FORMAT, \ multiplex:2, packetid1:2051, packetid2:2052, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2051.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2052.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2051.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2052.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.73, parent:DCB.MVD.7, type:ONCS_MVD, unit:3, sourceid:3d08, format:HIT_FORMAT, \ multiplex:2, packetid1:2053, packetid2:2054, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2053.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2054.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2053.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2054.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.74, parent:DCB.MVD.7, type:ONCS_MVD, unit:4, sourceid:4d08, format:HIT_FORMAT, \ multiplex:2, packetid1:2056, packetid2:2055, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2056.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2055.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2056.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2055.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.75, parent:DCB.MVD.7, unit:5, sourceid:5d08, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD //------------------------------------------------------------------------------- label:ONCS_DCB, name:DCB.MVD.8, parent:DCMGROUP.MVD.0, slot:10, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.81, parent:DCB.MVD.8, type:ONCS_MVD, unit:1, sourceid:1d09, format:HIT_FORMAT, \ multiplex:2, packetid1:2058, packetid2:2057, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2058.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2057.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2058.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2057.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.82, parent:DCB.MVD.8, type:ONCS_MVD, unit:2, sourceid:2d09, format:HIT_FORMAT, \ multiplex:2, packetid1:2060, packetid2:2059, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2060.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2059.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2060.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2059.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.83, parent:DCB.MVD.8, type:ONCS_MVD, unit:3, sourceid:3d09, format:HIT_FORMAT, \ multiplex:2, packetid1:2061, packetid2:2062, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2061.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2062.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2061.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2062.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.84, parent:DCB.MVD.8, type:ONCS_MVD, unit:4, sourceid:4d09, format:HIT_FORMAT, \ multiplex:2, packetid1:2064, packetid2:2063, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2064.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2063.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2064.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2063.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.85, parent:DCB.MVD.8, unit:5, sourceid:5d09, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD //------------------------------------------------------------------------------- //------------------------------------------------------------------------------- //------------------------------------------------------------------------------- // MVD boards - group b (corresponds to last 8 packets of inner layer, then outer layer, followed by pads) label:ONCS_PARTITIONER, name:DCMGROUP.MVD.1, controller:iocondev4b, index:1, file:$ONLINE_CONFIGURATION/Dcm/mvd_b_daq4b_1.dat, SEB_MVD_1 label:ONCS_PAR, name:PAR.MVD.1, parent:DCMGROUP.MVD.1, slot:21 label:ONCS_DCB, name:DCB.MVD.1, parent:DCMGROUP.MVD.1, slot:14, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.11, parent:DCB.MVD.1, type:ONCS_MVD, unit:1, sourceid:1d0d, format:HIT_FORMAT, \ multiplex:2, packetid1:2066, packetid2:2065, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2066.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2065.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2066.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2065.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.12, parent:DCB.MVD.1, type:ONCS_MVD, unit:2, sourceid:2d0d, format:HIT_FORMAT, \ multiplex:2, packetid1:2068, packetid2:2067, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2068.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2067.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2068.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2067.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.13, parent:DCB.MVD.1, type:ONCS_MVD, unit:3, sourceid:3d0d, format:HIT_FORMAT, \ multiplex:2, packetid1:2070, packetid2:2069, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2070.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2069.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2070.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2069.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.14, parent:DCB.MVD.1, type:ONCS_MVD, unit:4, sourceid:4d0d, format:HIT_FORMAT, \ multiplex:2, packetid1:2072, packetid2:2071, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2072.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2071.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2072.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2071.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.15, parent:DCB.MVD.1, unit:5, sourceid:5d0d, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD // outer barrel starts here: //------------------------------------------------------------------------------- label:ONCS_DCB, name:DCB.MVD.2, parent:DCMGROUP.MVD.1, slot:15, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.21, parent:DCB.MVD.2, type:ONCS_MVD, unit:1, sourceid:1d0e, format:HIT_FORMAT, \ multiplex:2, packetid1:2073, packetid2:2074, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2073.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2074.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2073.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2074.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.22, parent:DCB.MVD.2, type:ONCS_MVD, unit:2, sourceid:2d0e, format:HIT_FORMAT, \ multiplex:2, packetid1:2075, packetid2:2076, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2075.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2076.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2075.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2076.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.23, parent:DCB.MVD.2, type:ONCS_MVD, unit:3, sourceid:3d0e, format:HIT_FORMAT, \ multiplex:2, packetid1:2077, packetid2:2078, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2077.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2078.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2077.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2078.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.24, parent:DCB.MVD.2, type:ONCS_MVD, unit:4, sourceid:4d0e, format:HIT_FORMAT, \ multiplex:2, packetid1:2080, packetid2:2079, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2080.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2055.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2080.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2079.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.25, parent:DCB.MVD.2, unit:5, sourceid:5d0e, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD //------------------------------------------------------------------------------- label:ONCS_DCB, name:DCB.MVD.3, parent:DCMGROUP.MVD.1, slot:16, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.31, parent:DCB.MVD.3, type:ONCS_MVD, unit:1, sourceid:1d0f, format:HIT_FORMAT, \ multiplex:2, packetid1:2082, packetid2:2081, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2082.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2081.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2082.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2081.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.32, parent:DCB.MVD.3, type:ONCS_MVD, unit:2, sourceid:2d0f, format:HIT_FORMAT, \ multiplex:2, packetid1:2084, packetid2:2083, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2084.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2083.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2084.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2083.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.33, parent:DCB.MVD.3, type:ONCS_MVD, unit:3, sourceid:3d0f, format:HIT_FORMAT, \ multiplex:2, packetid1:2085, packetid2:2086, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2085.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2086.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2085.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2086.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.34, parent:DCB.MVD.3, type:ONCS_MVD, unit:4, sourceid:4d0f, format:HIT_FORMAT, \ multiplex:2, packetid1:2087, packetid2:2088, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2087.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2088.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2087.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2088.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.35, parent:DCB.MVD.3, unit:5, sourceid:5d0f, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD //------------------------------------------------------------------------------- label:ONCS_DCB, name:DCB.MVD.4, parent:DCMGROUP.MVD.1, slot:17, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.41, parent:DCB.MVD.4, type:ONCS_MVD, unit:1, sourceid:1d10, format:HIT_FORMAT, \ multiplex:2, packetid1:2089, packetid2:2090, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2089.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2090.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2089.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2090.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.42, parent:DCB.MVD.4, type:ONCS_MVD, unit:2, sourceid:2d10, format:HIT_FORMAT, \ multiplex:2, packetid1:2092, packetid2:2091, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2092.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2091.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2092.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2091.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.43, parent:DCB.MVD.4, type:ONCS_MVD, unit:3, sourceid:3d10, format:HIT_FORMAT, \ multiplex:2, packetid1:2094, packetid2:2093, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2094.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2093.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2094.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2093.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.44, parent:DCB.MVD.4, type:ONCS_MVD, unit:4, sourceid:4d10, format:HIT_FORMAT, \ multiplex:2, packetid1:2096, packetid2:2095, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2096.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2095.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2096.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2095.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.45, parent:DCB.MVD.4, unit:5, sourceid:5d10, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD //------------------------------------------------------------------------------- // start south pads label:ONCS_DCB, name:DCB.MVD.5, parent:DCMGROUP.MVD.1, slot:18, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.51, parent:DCB.MVD.5, type:ONCS_MVD, unit:1, sourceid:1d11, format:HIT_FORMAT, \ multiplex:2, packetid1:2098, packetid2:2099, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2098.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2099.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2098.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2099.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.52, parent:DCB.MVD.5, type:ONCS_MVD, unit:2, sourceid:2d11, format:HIT_FORMAT, \ multiplex:2, packetid1:2108, packetid2:2097, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2108.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2097.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2108.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2097.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.53, parent:DCB.MVD.5, type:ONCS_MVD, unit:3, sourceid:3d11, format:HIT_FORMAT, \ multiplex:2, packetid1:2106, packetid2:2107, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2106.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2107.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2106.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2107.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.54, parent:DCB.MVD.5, type:ONCS_MVD, unit:4, sourceid:4d11, format:HIT_FORMAT, \ multiplex:2, packetid1:2101, packetid2:2100, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2101.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2100.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2101.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2100.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.55, parent:DCB.MVD.5, unit:5, sourceid:5d11, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD //------------------------------------------------------------------------------- label:ONCS_DCB, name:DCB.MVD.6, parent:DCMGROUP.MVD.1, slot:19, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.61, parent:DCB.MVD.6, type:ONCS_MVD, unit:1, sourceid:1d12, format:HIT_FORMAT, \ multiplex:2, packetid1:2103, packetid2:2102, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2103.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2102.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2103.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2102.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.62, parent:DCB.MVD.6, type:ONCS_MVD, unit:2, sourceid:2d12, format:HIT_FORMAT, \ multiplex:2, packetid1:2105, packetid2:2104, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2105.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2104.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2105.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2104.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES // start north pads: label:ONCS_DCM_FE2, name:DCM.MVD.63, parent:DCB.MVD.6, type:ONCS_MVD, unit:3, sourceid:3d12, format:HIT_FORMAT, \ multiplex:2, packetid1:2110, packetid2:2111, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2110.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2111.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2110.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2111.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.64, parent:DCB.MVD.6, type:ONCS_MVD, unit:4, sourceid:4d12, format:HIT_FORMAT, \ multiplex:2, packetid1:2120, packetid2:2109, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2120.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2109.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2120.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2109.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.65, parent:DCB.MVD.6, unit:5, sourceid:5d12, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD //------------------------------------------------------------------------------- label:ONCS_DCB, name:DCB.MVD.7, parent:DCMGROUP.MVD.1, slot:20, level1dd:LEVEL1_HITFORMAT label:ONCS_DCM_FE2, name:DCM.MVD.71, parent:DCB.MVD.7, type:ONCS_MVD, unit:1, sourceid:1d13, format:HIT_FORMAT, \ multiplex:2, packetid1:2118, packetid2:2119, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2118.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2119.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2118.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2119.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.72, parent:DCB.MVD.7, type:ONCS_MVD, unit:2, sourceid:2d13, format:HIT_FORMAT, \ multiplex:2, packetid1:2113, packetid2:2112, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2113.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2112.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2113.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2112.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.73, parent:DCB.MVD.7, type:ONCS_MVD, unit:3, sourceid:3d13, format:HIT_FORMAT, \ multiplex:2, packetid1:2115, packetid2:2114, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2115.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2114.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2115.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2114.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DCM_FE2, name:DCM.MVD.74, parent:DCB.MVD.7, type:ONCS_MVD, unit:4, sourceid:4d13, format:HIT_FORMAT, \ multiplex:2, packetid1:2117, packetid2:2116, packetid3:0, packetid4:0, \ flag1:0, flag2:0, \ dsp:DCM_DSP_MVD, \ fpga:DCM_FPGA_MVD, \ list:DCM_LIST_MVD, \ threshold1:$DCM_THRESHOLDS/mvd/mvd2117.thresh, \ threshold2:$DCM_THRESHOLDS/mvd/mvd2116.thresh, \ pedestal1:$DCM_PEDESTALS/mvd/mvd2117.ped, \ pedestal2:$DCM_PEDESTALS/mvd/mvd2116.ped, \ calib1:cnull, \ calib2:cnull, \ readout:YES label:ONCS_DSP5, name:DCM.MVD.75, parent:DCB.MVD.7, unit:5, sourceid:5d13, \ flag1:0, flag2:0, \ dsp:DCM_DSP5_MVD, \ readout:YES //----------------- NO FURTHER INPUTS ------------------------------------------ //------------------------------------------------------------------------------- //------------------------------------------------------------------------------- //------------------------------------------------------------------------------- //-------------------------------------------------------------------------------